Analog Integrated Circuits and Signal Processing最新文献_第8页

Design and implementation of high-performance 20-T hybrid full adder circuit 高性能 20-T 混合全加法器电路的设计与实现

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-27 DOI: 10.1007/s10470-023-02219-y

Jyoti Kandpal, Abhishek Tomar

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A high-precision frequency measurement method combining π-type delay chain and different frequency phase coincidence detection 结合 π 型延迟链和不同频率相位重合检测的高精度频率测量方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-26 DOI: 10.1007/s10470-023-02220-5

Baoqiang Du, Wenming Li

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A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier 新型可逆门及半加法器、减法器和 2 位乘法器的优化实现

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-24 DOI: 10.1007/s10470-023-02224-1

Siddhesh Soyane, Ajay Kumar Kushwaha, Dhiraj Manohar Dhane

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Design and modeling of film bulk acoustic resonator considering temperature compensation for 5G communication 考虑温度补偿的薄膜体声谐振器设计与建模，用于 5G 通信

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-21 DOI: 10.1007/s10470-023-02210-7

Xiushan Wu, Lin Xu, Ge Shi, Xiaowei Zhou, Jianping Cai

{"title":"Design and modeling of film bulk acoustic resonator considering temperature compensation for 5G communication","authors":"Xiushan Wu, Lin Xu, Ge Shi, Xiaowei Zhou, Jianping Cai","doi":"10.1007/s10470-023-02210-7","DOIUrl":"10.1007/s10470-023-02210-7","url":null,"abstract":"<div><p>The new generation of communication systems requires radio frequency (RF) filters with better performance indicators, and traditional RF filters can no longer satisfy the requirements of increasingly sophisticated wireless communication equipment. Piezoelectric Film bulk acoustic resonators (FBARs) have gradually become a focus of communication system research. In this study, the temperature effect was considered in the FBAR electrical model. SiO<sub>2</sub> with a positive temperature coefficient was placed under the bottom electrode to perform temperature compensation. COMSOL software was used to study the shape of the electrode of the FBAR unit, the irregular shape of the electrode could obtain a smoother resonant frequency curve, and the common cavity and back erosion structure of the FBAR unit were studied, to extract the corresponding dielectric loss and mechanical loss of the piezoelectric layer, and to optimize the one-dimensional electrical model further. The optimized electrical model was used to design an FBAR filter. The center frequency was 3.52 GHz, the bandwidth was 115 MHz, the insertion loss was 0.87 dB, the in-band ripple was 1.32 dB, the out-of-band rejection was better than − 40 dB, and the absolute value of temperature coefficient of frequency was 7.09 ppm/°C, basically achieving the expected performance, which can be applied to the design of RF filters in mobile phones and other wireless terminals where the temperature requirement is harsh, and provides a solution for frequency selection and control in the field of high frequency communication.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138950039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Realization of a pseudo-random number generator utilizing two coupled Izhikevich neurons on an FPGA platform 在 FPGA 平台上利用两个耦合 Izhikevich 神经元实现伪随机数发生器

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-20 DOI: 10.1007/s10470-023-02223-2

Mohammad Saeed Feali

{"title":"Realization of a pseudo-random number generator utilizing two coupled Izhikevich neurons on an FPGA platform","authors":"Mohammad Saeed Feali","doi":"10.1007/s10470-023-02223-2","DOIUrl":"10.1007/s10470-023-02223-2","url":null,"abstract":"<div><p>Paired neurons exhibit diverse dynamic behaviors, including chaotic patterns. This paper presents an FPGA-based implementation of a high-speed pseudo-random number generator using two coupled Izhikevich oscillators. The dynamical characteristics of the neuronal model are investigated via MATLAB-based simulations, while the proposed generator is effectively modeled and simulated utilizing the Xilinx system generator framework. The model is then synthesized using the Xilinx Synthesis Tool followed by its implementation on the evaluation board of the Xilinx Spartan-6 XC6SLX9 FPGA. A post-processing procedure incorporating the exclusive OR operation has been employed to enhance the randomness of the output bits. The proposed pseudo-random number generator has a lower implementation cost compared to similar works, while achieving a maximum frequency of 49.6 MHz and a bit generation rate of 28.4 Mbit/s. The quality of the generated bit sequences is evaluated through various statistical analyses, including the scale index method, autocorrelation test, information entropy analysis, and the NIST test suite. The tests result demonstrate that the numbers generated through the proposed method exhibit a high entropy value, non-periodic behavior, and a lack of correlation. The proposed random number generator has potential applications in security and encryption systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138954387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A floating memristor emulator for analog and digital applications with experimental results 用于模拟和数字应用的浮动忆阻器仿真器及实验结果

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-19 DOI: 10.1007/s10470-023-02221-4

B. Suresha, Chandra Shankar, S. B. Rudraswamy

引用次数: 0

A novel memristor-based method to compute eigenpairs 基于记忆晶体管的特征对计算新方法

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-19 DOI: 10.1007/s10470-023-02214-3

Hongxiao Zhao, Zezhi Cheng, Chujun Han, Hongxuan Guo, Litao Sun

{"title":"A novel memristor-based method to compute eigenpairs","authors":"Hongxiao Zhao, Zezhi Cheng, Chujun Han, Hongxuan Guo, Litao Sun","doi":"10.1007/s10470-023-02214-3","DOIUrl":"10.1007/s10470-023-02214-3","url":null,"abstract":"<div><p>Although digital processors offer high computing accuracy, they suffer enormously from lengthy execution times and high energy consumption as a result of the numerous communications between the processors and storage units. The disadvantage is especially acute when performing data-intensive operations, such as deep neural networks and matrix operations. To address this, several novel ideas and devices for implementing in-memory computing have been proposed. One of them is the memristor. Because of their scalability, nonvolatility, and analog storage characteristics, memristors have considerable potential and have achieved some encouraging research results. An eigenpair estimation method and a memristor-based crossbar structure are presented in this paper. The method differs from conventional computers in that the execution is carried out with the least number of controls and data transfers as possible. Almost all of the desired outcomes can be attributed to fundamental physical laws, such as Ohm’s law and Kirchhoff’s law. This method is then applied to principal component analysis (PCA) in the end.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138816647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process 在 180 纳米 CMOS 工艺中设计具有低功耗和高工作频率范围特性的延迟锁定环路

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-19 DOI: 10.1007/s10470-023-02203-6

Fatemeh Esmaili Saraji, Alireza Ghorbani, Seyed Mahmoud Anisheh

{"title":"Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process","authors":"Fatemeh Esmaili Saraji, Alireza Ghorbani, Seyed Mahmoud Anisheh","doi":"10.1007/s10470-023-02203-6","DOIUrl":"10.1007/s10470-023-02203-6","url":null,"abstract":"<div><p>A delay lock loop is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on a CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques with good current matching. The delay cell uses the bulk-driven technique and has less power consumption than the conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138816453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hard-disk drive read-channel design trade-offs for areal densities beyond 2 Tb/in2 面积密度超过 2 Tb/in2 的硬盘驱动器读取通道设计取舍

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-18 DOI: 10.1007/s10470-023-02198-0

Tertulien Ndjountche

引用次数: 0

Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise 基于近似加法器和近似乘法器的节能型增强全通变换可变数字滤波器设计，用于消除传感器节点噪声

IF 1.2 4区工程技术

Analog Integrated Circuits and Signal Processing Pub Date : 2023-12-17 DOI: 10.1007/s10470-023-02201-8

M. Ramkumar Raja, R. Naveen, C. Anand Deva Durai, Mohammed Usman, Neeraj Kumar Shukla, Mohammed Abdul Muqeet

{"title":"Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise","authors":"M. Ramkumar Raja, R. Naveen, C. Anand Deva Durai, Mohammed Usman, Neeraj Kumar Shukla, Mohammed Abdul Muqeet","doi":"10.1007/s10470-023-02201-8","DOIUrl":"10.1007/s10470-023-02201-8","url":null,"abstract":"<div><p>Variable digital filter (VDF) plays a significant role in communication and signal processing field. Any prototype filter's preferred frequency response is attained by creating All Pass Transformation (APT) based filter to maintain complete control over the cut-off frequency. However, the speed, power, and area usage of the digital filter are constrained by its performance. Therefore, in this manuscript, All Pass Transformation based Variable digital filters (APT-VDF) using Error Reduced Carry Prediction Approximate Adder (ERCPAA) andSandpiper Optimization fostered Approximate Multiplier (SO-AM) is proposed. The proposed APT-VDF-ERCPAA-SOAM filter design is utilized for enhancing the filter efficiency by reducing noise in the sensor nodes. The proposed ERCPAA design is incorporated with carry prediction and constant truncation for diminishing the path delay and area utilization. Moreover, the proposed SO-AM is used for minimizing the design complexity and power utilization. The simulation of the proposed method is activated in Verilog and the design is synthesized in FPGA uses Xilinx ISE 14.5. The proposed APT-VDF- ERCPAA- SO-AM filter design has attained 35.6%, 21.75%, 28.69% lower power and 46.58%, 12.3%, 38.07% lower delay than the existing approaches, like Very Large-Scale Integration design of All Pass Transformation based Variable digital filters uses a new variable block sized ternary adder (VBSTA) and ternary multiplier (APTVDF-VBSTA-TM), Finite Impulse Response (FIR) adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture (FIR- CSDABR-DA) and digital FIR filter design using Carry Save Adder (CSA) and Structured Tree Multiplier (FIR-CSA-STM) respectively.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":null,"pages":null},"PeriodicalIF":1.2,"publicationDate":"2023-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138686439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0