Analog Integrated Circuits and Signal Processing最新文献

{"title":"ADAS radar antenna for mmW/THz communication","authors":"Sapna Chaudhary,&nbsp;Ankush Kansal","doi":"10.1007/s10470-025-02448-3","DOIUrl":"10.1007/s10470-025-02448-3","url":null,"abstract":"<div><p>Antenna for advanced driving assistance system (ADAS) is a progressive field of research that introduces the intelligent and autonomous attributes in modern vehicles to deliver increased safety and comfort. ADAS includes passive and active safety system that is designed to reduce the road fatalities by minimizing human error. Here, a microstrip-fed compact triband printed antenna is investigated for the system possessing 75.5–80.2 GHz, 93.6–100.5 GHz and 116.5–129.5 GHz frequency range and thus covers the standard 77/94/122 GHz bands. The antenna has an extremely compact size of (2 × 2 × 0.288 mm³) and is printed on the substrate RO4350B. By etching a series of closed and open-ended slots, triband characteristics are achieved by exciting the TM₀₁, TM₁₀ and TM₁₁ modes at the desired resonant frequencies. The proposed structure is first of its kinds and shows 85%, 89.2% and 76.4% of radiating efficiency with the gain of 6.43 dBi, 5.43 dBi and 8.07 dBi at 77.7 GHz, 97.4 GHz and 124.7 GHz respectively and can be potentially used for autonomous driving and ADAS System applications. Nevertheless, a multiple input multiple output design is proposed for the antenna to improve the data rate, link reliability and reduce multipath fading. Its parameters like isolation, diversity gain, envelope correlation and channel capacity loss validate its performance for MIMO applications also. In addition, lumped element RLC circuit of the proposed antenna is designed and evaluated.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145166657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DTMOS based mixed active building blocks for current-mode third-order sinusoidal oscillator design","authors":"Gandikota Naga Chandrika,&nbsp;Gurumurthy Komanapalli","doi":"10.1007/s10470-025-02434-9","DOIUrl":"10.1007/s10470-025-02434-9","url":null,"abstract":"<div><p>This study designs a current mode (CM) third-order sinusoidal oscillator using various active building blocks (ABBs), including a voltage difference transconductance amplifier (VDTA) and a plus-type differential difference current conveyor (+DDCC). The construction of the system involved the utilization of one resistor connected to the ground and three capacitors connected to the ground. In addition, the proposed third-order sinusoidal oscillator is designed using dynamic threshold metal oxide semiconductor (DTMOS) technology to achieve minimal power consumption due to leakage. In the proposed circuit, input bias currents are applied to control the oscillation condition (CO) and frequency of oscillation (FO) in an electronically/orthogonally manner. Also, the proposed circuit is suitable for integrated circuits (ICs) as it is designed with only grounded active elements. Subsequently, the circuit’s overall power consumption is reduced by the usage of 0.6 Volts (V) supply voltage. Using the Cadence virtuoso GPDK 90nm technology, various performance analyses are performed to validate the efficiency of the proposed circuit. When compared to other designs, the proposed circuit consumes a power consumption of 48 <span>(mu W)</span>, and its total harmonic distortion (THD) ranges from 2.8% to 3.3%, which is within acceptable bounds.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145166431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A battery-less hybrid in-tire pressure monitoring SOC for road vehicles using adaptive bayesian system and optimized wireless communication model","authors":"A. Vasantharaj,&nbsp;N. Nandhagopal,&nbsp;Ramya Murugesan,&nbsp;O. Cyril Mathew","doi":"10.1007/s10470-025-02418-9","DOIUrl":"10.1007/s10470-025-02418-9","url":null,"abstract":"<div><p>Modern automobile battery management systems are becoming more and more susceptible to cyberattacks, which may compromise system performance, safety, and efficiency. These security risks are frequently ignored by existing tire pressure monitoring system (TPMS) solutions while preserving power efficiency. In order to address these obstacles, this study suggests a battery-free hybrid in-tire pressure monitoring system-on-chip (SoC) that combines an improved wireless communication model to improve security and power efficiency with an adaptive Bayesian system for secure data fusion. This adaptive Bayesian system estimation is utilized to fuse the multi-sensor data to minimize the uncertainty of the calculation. It enhances the system’s accuracy by reducing data redundancy. It also deals with the imprecision of sensory assessment because of the noise in the environment and feasible hardware malfunction. The wireless transmission link consists of a transmitter and receiver in the second phase. To establish the reliability of the wireless communication method, in tire data transmitter and receiver are constructed. After that, it moves on to the data connection link between the transmitter and receiver to send and receive the necessary temperature and pressure data. Improving the voltage-controlled oscillator (VCO) in the transmitter module is one way to lessen power consumption and phase noise in the PLL architecture. The major concern of this proposed battery less hybrid TPMS is to reduce the core power and effectively enhance the performance of the SoC of TPMS. The performance metrics used in this research are the measurement of fusion errors, utilization of power in pressure and temperature sensors, the transmitter phase noise and the output spectrum. Also, area, efficiency, frequency and output power are evaluated to prove the effectiveness of the proposed battery less hybrid TPMS Soc. In addition, the VCO’s efficiency, output power, phase noise, and frequency tuning range are analyzed.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145166447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-performance flipped voltage follower based low input resistance current mirror with wide current mirroring range and high output resistance","authors":"Rishikesh Pandey,&nbsp;Caffey Jindal","doi":"10.1007/s10470-025-02432-x","DOIUrl":"10.1007/s10470-025-02432-x","url":null,"abstract":"<div><p>This paper presents a high performance current mirror with a large current mirroring range. The advantages of folded flipped voltage follower (FVF) cell and super cascode transistor are combined in proposed current mirror, which make it suitable for high performance applications. The folded FVF cell provides low resistance node which is utilized to inject the input current and therefore, proposed current mirror shows input resistance of 24.15 Ω. By employing a super cascode transistor at the output node, the output resistance is increased to 28.3 GΩ. The presented current mirror achieves bandwidth of 280 MHz and wide current mirroring range of 0 to 500 µA. The proposed current mirror has been designed using 0.18 µm CMOS technology and simulated using spectre in Cadence Virtuoso Analog Design Environment. The physical layout is designed using Cadence Virtuoso layout XL editor. The efficiency of the proposed current mirror has been demonstrated by post-layout simulation results.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145166659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Smart capacitance sensing system on flexible substrate using oxide TFTs","authors":"Suyash Shrivastava,&nbsp;Pydi Ganga Bahubalindruni,&nbsp;Nishtha Kansal,&nbsp;Pedro Barquinha","doi":"10.1007/s10470-025-02437-6","DOIUrl":"10.1007/s10470-025-02437-6","url":null,"abstract":"<div><p>This paper presents a novel smart capacitance sensing/detection system using amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) technology. Proposed system and the individual blocks have been fabricated on a 30 <span>(mu)</span>m thick flexible polyimide substrate. This system employs a C–V converter and a bootstrapped pseudo CMOS based latched comparator. Individual circuits and full system have been characterized from measurements under normal ambient conditions at a supply voltage (<span>(V_{DD})</span>) of 4 <span>(textrm{V})</span>. The sensitivity of the C–V converter is 6.5 <span>(mathrm {mV/pF})</span>. Comparator is showing <span>(f_{inmax})</span> of 12 <span>(textrm{kHz})</span>, power consumption of 20 <span>(mu)</span>W at a <span>(f_{clk})</span> of ten times of <span>(f_{inmax})</span>. The proposed system can detect a change in capacitance down to 5 <span>(textrm{pF})</span> with a power consumption of around 20.5 <span>(mu)</span>W. This work finds potential applications in systems, which needs smart sensing, such as, compact wearable devices, smart packaging, and preventive healthcare by significantly reducing the risk of inhaling toxic gases present in environment, whose concentration levels can be sensed in terms of capacitance. </p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145164889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An intuitionistic model for evaluating the dopant profiles in C-BAs MOSFETs: integrating capacitance–voltage method for large scale applications","authors":"Harikrishnan Perumalsamy,&nbsp;Sivakumar Pothiraj,&nbsp;Suresh Muthusamy,&nbsp;Anuraj Singh","doi":"10.1007/s10470-025-02425-w","DOIUrl":"10.1007/s10470-025-02425-w","url":null,"abstract":"<div><p>This study aims to perform a comprehensive assessment of the influence of dopant profile variations such as junction features, variability, and uniformity in C-BAs substrate MOSFET devices with other semiconductor materials using Sentaurus TCAD. The principal objective of our inquiry is to establish the efficacy and reliability of C-BAs MOSFETs in the face of real-world challenges, thereby providing valuable insights into their robustness and reliability. To initiate our exploration, by conducting a detailed scrutiny of C-BAs MOSFET technology, with a particular focus on emerging issues related to persistence and side-channel attacks. Subsequently, a particular examination of the dopant profile will be carried out through a well-selected sample set, followed by the application of C–V methodology for dopant profile characterization. By following this methodology, potential opportunities for enhancing the security of C-BAs MOSFETs can be identified, thus laying the groundwork for future research endeavors in the field of semiconductor device design.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145164886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ultra low power and fast tuning interpolator in digital controlled oscillator for all digital phase locked loop","authors":"Syaza Norfilsha Ishak,&nbsp;Jahariah Sampe,&nbsp;Nazrul Anuar Nayan,&nbsp;Huda Abdullah,&nbsp;Noor Hidayah Mohd Yunus,&nbsp;Mohammad Faseehuddin","doi":"10.1007/s10470-025-02416-x","DOIUrl":"10.1007/s10470-025-02416-x","url":null,"abstract":"<div><p>All-digital phase-locked loops (ADPLL) have become increasingly attractive to academicians and industries in system-on-chips applications due to advancements in complementary metal-oxide-semiconductor (CMOS) technology, particularly in terms of reduced power consumption and smaller chip area. In ADPLL, the most vital component is the digital oscillator design, which comprises a coarse-tuned part and a fine-tuned part. This work focuses specifically on the fine-tuning part to enhance the power dissipation performance of the digital oscillator in the ADPLL. The interpolation technique is employed in circuit design, utilizing two types of controllable inverter configurations with proper sizing of CMOS within a single stage. The interpolator fine-tuned circuit consists of seven stages and is controlled by a 6-bit phase control input. This design achieves a phase step of 6 ps to 31 ps, with a power dissipation of 0.09 <span>(mu)</span>W at a supply voltage of 1.2 V. The circuit is implemented using the Silterra 130 nm technology process, and the post-layout design achieves a compact dimension of 0.00789 <span>(hbox {mm}^2)</span>.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145164201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A low-power, full-custom design of a 4:2 compressor using 32 nm CNTFET technology for high-speed signal processing","authors":"K. Gavaskar,&nbsp;S. Elango,&nbsp;Gopinath Palanisamy,&nbsp;N. Adhithyaa,&nbsp;A. Srinath","doi":"10.1007/s10470-025-02439-4","DOIUrl":"10.1007/s10470-025-02439-4","url":null,"abstract":"<div><p>Multiplication is a vital function in most Digital Signal Processing (DSP) applications. In general, multipliers take-up more space, have longer latency, and use more energy than other types of digital circuits. This paper will discuss the design of compressors and performance comparisons with respect to size, power, and speed. Compressors are the essential parts of multipliers that allow for the parallel accumulation and reduction of incomplete product stages. Enhancing the compressor’s performance has an impact on the multiplier’s capacity, which has an impact on the DSP’s effectiveness. The Carbon Nanotube Field Effect Transistor (CNTFET) has benefited from the Fin Field-Effect Transistor (FinFET) because carbon nanotubes are the stiffest and sturdiest materials. Due to its superior regularization and reduced complexity, the compressor structure is generally selected among the other varieties. Partial product terms are condensed using a compressor into two operands in Partial Product Reduction (PPR). A new design for a compressor is proposed and tested. The performance of this new compressor is simulated and checked to that of existing ones using Cadence’s Virtuoso tool, with 32 nm CNTFET technology. Simulation outcomes confirm that the projected compressor reduces delay by 10.31%, EDP by 30.82%, and PDP by 25.09%, outperforming existing ones.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145165549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and implementation of cost-effective flexible paper based Wi-Fi sensor for commercial applications","authors":"Nithya S,&nbsp;Sujatha V,&nbsp;Rama Prabha K P,&nbsp;Saravanan V","doi":"10.1007/s10470-025-02433-w","DOIUrl":"10.1007/s10470-025-02433-w","url":null,"abstract":"<div><p>In recent days, it has been mandatory to embed sensors in almost all electronic products to make the products as smart gadgets. RF systems play a key role in enhancing the sensing capability of those gadgets in easier and affordable way. RF sensors defined to be resonated at the designated frequency is considered accurate within the bandlimit. RF sensors manufactured are high in demand in sensing wi-fi signals, when moving in anonymous regions. The demand gives an idea of developing a flexible wi-fi sensor with microstrip-coplanar waveguide-microstrip configuration on a paper substrate, for affordable applications. The sensor utilizes band pass characteristics at 2.45 GHz band over a bandwidth of 320 MHz. The design of the proposed sensor utilizes 60.5 × 30 × 0.358 mm³ volume. The proposed chip-less passive prototype will be advantageous in many commercial applications and cheaper one if manufactured in bulk.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145164887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improved low noise and highly linear 5–6 GHz LNA for Wi-Fi 6/6E-IEEE 802.11ax standard 5G application","authors":"V. Thenmozhi,&nbsp;M. Bhaskar","doi":"10.1007/s10470-025-02436-7","DOIUrl":"10.1007/s10470-025-02436-7","url":null,"abstract":"<div><p>This paper proposes a wideband high linear LNA for multi-user applications that adopts a bootstrapped resonant circuit at the input terminal to provide better impedance matching with improved linearity performance. This LNA eliminates narrowband limitations and aims to bring high bandwidth, low noise, and maximum gain with high linearity. The proposed LNA design and implementation is carried out in UMC 180 nm CMOS process technology, and its characteristics are verified with post-layout simulations. In 5–6 GHz frequency, the LNA attains a maximum gain of 23.65 dB, lower Noise Figure of 2.5 dB, and an input return loss of − 35.1 dB with the power consumption of 9.73 mW from a 1.8 V supply. The IIP2 and IIP3 of LNA achieve a maximum of 14.22 dBm and + 6.78 dBm at the frequency of 5.3 GHz with unconditional stability for a wide range and attains better Figure of Merits (FoM) compared to the recently proposed LNAs in the literature. This proposed LNA is highly suited for high bandwidth and reduced congestion wireless applications like multi-user IEEE 802.11ax called High-Efficiency Wireless (HEW) systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145164888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}