{"title":"基于DTMOS的电流型三阶正弦振荡器混合有源模块设计","authors":"Gandikota Naga Chandrika, Gurumurthy Komanapalli","doi":"10.1007/s10470-025-02434-9","DOIUrl":null,"url":null,"abstract":"<div><p>This study designs a current mode (CM) third-order sinusoidal oscillator using various active building blocks (ABBs), including a voltage difference transconductance amplifier (VDTA) and a plus-type differential difference current conveyor (+DDCC). The construction of the system involved the utilization of one resistor connected to the ground and three capacitors connected to the ground. In addition, the proposed third-order sinusoidal oscillator is designed using dynamic threshold metal oxide semiconductor (DTMOS) technology to achieve minimal power consumption due to leakage. In the proposed circuit, input bias currents are applied to control the oscillation condition (CO) and frequency of oscillation (FO) in an electronically/orthogonally manner. Also, the proposed circuit is suitable for integrated circuits (ICs) as it is designed with only grounded active elements. Subsequently, the circuit’s overall power consumption is reduced by the usage of 0.6 Volts (V) supply voltage. Using the Cadence virtuoso GPDK 90nm technology, various performance analyses are performed to validate the efficiency of the proposed circuit. When compared to other designs, the proposed circuit consumes a power consumption of 48 <span>\\(\\mu W\\)</span>, and its total harmonic distortion (THD) ranges from 2.8% to 3.3%, which is within acceptable bounds.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4000,"publicationDate":"2025-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DTMOS based mixed active building blocks for current-mode third-order sinusoidal oscillator design\",\"authors\":\"Gandikota Naga Chandrika, Gurumurthy Komanapalli\",\"doi\":\"10.1007/s10470-025-02434-9\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This study designs a current mode (CM) third-order sinusoidal oscillator using various active building blocks (ABBs), including a voltage difference transconductance amplifier (VDTA) and a plus-type differential difference current conveyor (+DDCC). The construction of the system involved the utilization of one resistor connected to the ground and three capacitors connected to the ground. In addition, the proposed third-order sinusoidal oscillator is designed using dynamic threshold metal oxide semiconductor (DTMOS) technology to achieve minimal power consumption due to leakage. In the proposed circuit, input bias currents are applied to control the oscillation condition (CO) and frequency of oscillation (FO) in an electronically/orthogonally manner. Also, the proposed circuit is suitable for integrated circuits (ICs) as it is designed with only grounded active elements. Subsequently, the circuit’s overall power consumption is reduced by the usage of 0.6 Volts (V) supply voltage. Using the Cadence virtuoso GPDK 90nm technology, various performance analyses are performed to validate the efficiency of the proposed circuit. When compared to other designs, the proposed circuit consumes a power consumption of 48 <span>\\\\(\\\\mu W\\\\)</span>, and its total harmonic distortion (THD) ranges from 2.8% to 3.3%, which is within acceptable bounds.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":\"124 2\",\"pages\":\"\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-06-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-025-02434-9\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-025-02434-9","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
摘要
本研究采用多种有源模块(ABBs)设计了一个电流模式(CM)三阶正弦振荡器,包括电压差跨导放大器(VDTA)和加型差分电流传送带(+DDCC)。该系统的结构包括利用一个电阻连接到地,三个电容器连接到地。此外,所提出的三阶正弦振荡器采用动态阈值金属氧化物半导体(DTMOS)技术设计,以实现最小的泄漏功耗。在所提出的电路中,输入偏置电流以电子/正交方式控制振荡条件(CO)和振荡频率(FO)。此外,所提出的电路适用于集成电路(ic),因为它只设计了接地的有源元件。随后,电路的总功耗通过使用0.6伏(V)供电电压而降低。采用Cadence virtuoso GPDK 90nm技术,进行了各种性能分析以验证所提出电路的效率。与其他设计相比,所提出的电路功耗为48 \(\mu W\),其总谐波失真(THD)范围为2.8% to 3.3%, which is within acceptable bounds.
DTMOS based mixed active building blocks for current-mode third-order sinusoidal oscillator design
This study designs a current mode (CM) third-order sinusoidal oscillator using various active building blocks (ABBs), including a voltage difference transconductance amplifier (VDTA) and a plus-type differential difference current conveyor (+DDCC). The construction of the system involved the utilization of one resistor connected to the ground and three capacitors connected to the ground. In addition, the proposed third-order sinusoidal oscillator is designed using dynamic threshold metal oxide semiconductor (DTMOS) technology to achieve minimal power consumption due to leakage. In the proposed circuit, input bias currents are applied to control the oscillation condition (CO) and frequency of oscillation (FO) in an electronically/orthogonally manner. Also, the proposed circuit is suitable for integrated circuits (ICs) as it is designed with only grounded active elements. Subsequently, the circuit’s overall power consumption is reduced by the usage of 0.6 Volts (V) supply voltage. Using the Cadence virtuoso GPDK 90nm technology, various performance analyses are performed to validate the efficiency of the proposed circuit. When compared to other designs, the proposed circuit consumes a power consumption of 48 \(\mu W\), and its total harmonic distortion (THD) ranges from 2.8% to 3.3%, which is within acceptable bounds.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.