改进的低噪声和高线性5-6 GHz LNA,适用于Wi-Fi 6/6E-IEEE 802.11ax标准5G应用

IF 1.4 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
V. Thenmozhi, M. Bhaskar
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引用次数: 0

摘要

本文提出了一种适用于多用户应用的宽带高线性LNA,该LNA在输入端采用自举谐振电路,在提高线性性能的同时提供更好的阻抗匹配。该LNA消除了窄带限制,旨在实现高带宽、低噪声和高线性度的最大增益。采用联华电子180nm CMOS工艺进行了LNA的设计与实现,并通过布局后仿真验证了其特性。在5-6 GHz频率下,LNA的最大增益为23.65 dB,噪声系数为2.5 dB,输入回波损耗为−35.1 dB, 1.8 V电源功耗为9.73 mW。LNA的IIP2和IIP3在5.3 GHz频率下达到最大14.22 dBm和+ 6.78 dBm,在宽范围内具有无条件稳定性,与文献中最近提出的LNA相比,具有更好的优点图(FoM)。这种提议的LNA非常适合高带宽和减少拥塞的无线应用,如多用户IEEE 802.11ax称为高效无线(HEW)系统。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

Improved low noise and highly linear 5–6 GHz LNA for Wi-Fi 6/6E-IEEE 802.11ax standard 5G application

Improved low noise and highly linear 5–6 GHz LNA for Wi-Fi 6/6E-IEEE 802.11ax standard 5G application

This paper proposes a wideband high linear LNA for multi-user applications that adopts a bootstrapped resonant circuit at the input terminal to provide better impedance matching with improved linearity performance. This LNA eliminates narrowband limitations and aims to bring high bandwidth, low noise, and maximum gain with high linearity. The proposed LNA design and implementation is carried out in UMC 180 nm CMOS process technology, and its characteristics are verified with post-layout simulations. In 5–6 GHz frequency, the LNA attains a maximum gain of 23.65 dB, lower Noise Figure of 2.5 dB, and an input return loss of − 35.1 dB with the power consumption of 9.73 mW from a 1.8 V supply. The IIP2 and IIP3 of LNA achieve a maximum of 14.22 dBm and + 6.78 dBm at the frequency of 5.3 GHz with unconditional stability for a wide range and attains better Figure of Merits (FoM) compared to the recently proposed LNAs in the literature. This proposed LNA is highly suited for high bandwidth and reduced congestion wireless applications like multi-user IEEE 802.11ax called High-Efficiency Wireless (HEW) systems.

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来源期刊
Analog Integrated Circuits and Signal Processing
Analog Integrated Circuits and Signal Processing 工程技术-工程:电子与电气
CiteScore
0.30
自引率
7.10%
发文量
141
审稿时长
7.3 months
期刊介绍: Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today. A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.
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