{"title":"改进的低噪声和高线性5-6 GHz LNA,适用于Wi-Fi 6/6E-IEEE 802.11ax标准5G应用","authors":"V. Thenmozhi, M. Bhaskar","doi":"10.1007/s10470-025-02436-7","DOIUrl":null,"url":null,"abstract":"<div><p>This paper proposes a wideband high linear LNA for multi-user applications that adopts a bootstrapped resonant circuit at the input terminal to provide better impedance matching with improved linearity performance. This LNA eliminates narrowband limitations and aims to bring high bandwidth, low noise, and maximum gain with high linearity. The proposed LNA design and implementation is carried out in UMC 180 nm CMOS process technology, and its characteristics are verified with post-layout simulations. In 5–6 GHz frequency, the LNA attains a maximum gain of 23.65 dB, lower Noise Figure of 2.5 dB, and an input return loss of − 35.1 dB with the power consumption of 9.73 mW from a 1.8 V supply. The IIP2 and IIP3 of LNA achieve a maximum of 14.22 dBm and + 6.78 dBm at the frequency of 5.3 GHz with unconditional stability for a wide range and attains better Figure of Merits (FoM) compared to the recently proposed LNAs in the literature. This proposed LNA is highly suited for high bandwidth and reduced congestion wireless applications like multi-user IEEE 802.11ax called High-Efficiency Wireless (HEW) systems.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 2","pages":""},"PeriodicalIF":1.4000,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Improved low noise and highly linear 5–6 GHz LNA for Wi-Fi 6/6E-IEEE 802.11ax standard 5G application\",\"authors\":\"V. Thenmozhi, M. Bhaskar\",\"doi\":\"10.1007/s10470-025-02436-7\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper proposes a wideband high linear LNA for multi-user applications that adopts a bootstrapped resonant circuit at the input terminal to provide better impedance matching with improved linearity performance. This LNA eliminates narrowband limitations and aims to bring high bandwidth, low noise, and maximum gain with high linearity. The proposed LNA design and implementation is carried out in UMC 180 nm CMOS process technology, and its characteristics are verified with post-layout simulations. In 5–6 GHz frequency, the LNA attains a maximum gain of 23.65 dB, lower Noise Figure of 2.5 dB, and an input return loss of − 35.1 dB with the power consumption of 9.73 mW from a 1.8 V supply. The IIP2 and IIP3 of LNA achieve a maximum of 14.22 dBm and + 6.78 dBm at the frequency of 5.3 GHz with unconditional stability for a wide range and attains better Figure of Merits (FoM) compared to the recently proposed LNAs in the literature. This proposed LNA is highly suited for high bandwidth and reduced congestion wireless applications like multi-user IEEE 802.11ax called High-Efficiency Wireless (HEW) systems.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":\"124 2\",\"pages\":\"\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-025-02436-7\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-025-02436-7","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
Improved low noise and highly linear 5–6 GHz LNA for Wi-Fi 6/6E-IEEE 802.11ax standard 5G application
This paper proposes a wideband high linear LNA for multi-user applications that adopts a bootstrapped resonant circuit at the input terminal to provide better impedance matching with improved linearity performance. This LNA eliminates narrowband limitations and aims to bring high bandwidth, low noise, and maximum gain with high linearity. The proposed LNA design and implementation is carried out in UMC 180 nm CMOS process technology, and its characteristics are verified with post-layout simulations. In 5–6 GHz frequency, the LNA attains a maximum gain of 23.65 dB, lower Noise Figure of 2.5 dB, and an input return loss of − 35.1 dB with the power consumption of 9.73 mW from a 1.8 V supply. The IIP2 and IIP3 of LNA achieve a maximum of 14.22 dBm and + 6.78 dBm at the frequency of 5.3 GHz with unconditional stability for a wide range and attains better Figure of Merits (FoM) compared to the recently proposed LNAs in the literature. This proposed LNA is highly suited for high bandwidth and reduced congestion wireless applications like multi-user IEEE 802.11ax called High-Efficiency Wireless (HEW) systems.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.