A low-power, full-custom design of a 4:2 compressor using 32 nm CNTFET technology for high-speed signal processing

Multiplication is a vital function in most Digital Signal Processing (DSP) applications. In general, multipliers take-up more space, have longer latency, and use more energy than other types of digital circuits. This paper will discuss the design of compressors and performance comparisons with respect to size, power, and speed. Compressors are the essential parts of multipliers that allow for the parallel accumulation and reduction of incomplete product stages. Enhancing the compressor’s performance has an impact on the multiplier’s capacity, which has an impact on the DSP’s effectiveness. The Carbon Nanotube Field Effect Transistor (CNTFET) has benefited from the Fin Field-Effect Transistor (FinFET) because carbon nanotubes are the stiffest and sturdiest materials. Due to its superior regularization and reduced complexity, the compressor structure is generally selected among the other varieties. Partial product terms are condensed using a compressor into two operands in Partial Product Reduction (PPR). A new design for a compressor is proposed and tested. The performance of this new compressor is simulated and checked to that of existing ones using Cadence’s Virtuoso tool, with 32 nm CNTFET technology. Simulation outcomes confirm that the projected compressor reduces delay by 10.31%, EDP by 30.82%, and PDP by 25.09%, outperforming existing ones.