VLSI architecture of a True Random Number Generator with hierarchical Von Neumann corrector and hybrid run length-Golomb coding for data compression

Abstract

High-quality random number generation is necessary to ensure safe communication by preventing predictable encryption key patterns. This study introduces a new True Random Number Generator (TRNG) architecture that uses an efficient post-processing pipeline in conjunction with an entropy source based on a Digital Clock Manager (DCM). The proposed TRNG compresses random sequences using a Hybrid Run Length-Golomb Coding (HRL-GC) technique, reducing power consumption and increasing efficiency, and employs a Hierarchical Von Neumann Corrector (HVNC) to successfully remove bias while maintaining entropy. In contrast to traditional TRNGs, which have limited throughput and high power consumption, the proposed paradigm offers significant improvements in hardware utilization and performance. The proposed TRNG’s FPGA-based implementation outperforms state-of-the-art systems with a 35.13% improvement in throughput and power consumption of only 0.016 W. These results establish the proposed TRNG as a highly efficient and scalable solution for cryptographic applications, hardware security, and secure communication protocols.