Parasitic RC estimation and defect prediction for embedded memory using machine learning

Abstract

In today's rapidly scaling-down technological environment, identifying the best-fit algorithms for evaluating complicated circuits such as SRAMs is a difficult issue. Many fault models have developed, however their flexibility of use is limited by the restrictions and constraints of the provided test environment. The majority of existing fault models have been studied in terms of well-known March algorithms, which simply provide fault detection information. Scaled-down technologies have an impact on parasitic effects as well, resulting in an extra source of defective behavior and making current test algorithms vulnerable to them. Recent work that uses method of parasitic extraction for fault detection have addressed the problem of limitation due to scale down technologies. However, as the circuit complexity increases the estimation of RC would be tedious. Hence in this paper machine learning based parasitic RC extraction is proposed. Also, as an extension to that, proposed ML based fault detection using extracted parasitic RCs as dataset. The proposed machine learning based fault prediction uses extracted parasitic RCs as dataset. The parasitic RC values are extracted for each fault model using technologies of 120 nm down to deep submicron 7 nm. Regression algorithm is used for modeling the machine for extraction of RCs and observed that 88% of prediction accuracy. Decision tree modeling is used for fault detection and observed 91.7% of accuracy in prediction of fault.