{"title":"具有低温系数、低功耗和高PSRR的亚阈值CMOS电压基准","authors":"Shubing Wan, Hua Wu, Jiawei Cheng, Xianguo Cao","doi":"10.1007/s10470-025-02421-0","DOIUrl":null,"url":null,"abstract":"<div><p>This paper proposes a subthreshold CMOS voltage reference circuit. The design comprises a start-up circuit, a bias current generator, and a voltage subtraction output stage. Fabricated in a 0.18 µm CMOS process, the circuit achieves a power consumption of 17 nW at 27 °C with a supply voltage ranging from 1 to 3 V. At <i>V</i><sub>DD</sub> = 1.8 V, the output reference voltage (<i>V</i><sub>REF</sub>) is 297.3 mV, exhibiting a temperature coefficient (TC) of 2.565 ppm/°C over a temperature range of from − 40 to 125 °C. The power supply ripple rejection ratio (PSRR) at 10 Hz is − 102.9 dB. The proposed architecture demonstrates advantages in low-power consumption, compact area, and stable output performance.</p></div>","PeriodicalId":7827,"journal":{"name":"Analog Integrated Circuits and Signal Processing","volume":"124 1","pages":""},"PeriodicalIF":1.4000,"publicationDate":"2025-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A subthreshold CMOS voltage reference with low temperature coefficient, low power and high PSRR\",\"authors\":\"Shubing Wan, Hua Wu, Jiawei Cheng, Xianguo Cao\",\"doi\":\"10.1007/s10470-025-02421-0\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>This paper proposes a subthreshold CMOS voltage reference circuit. The design comprises a start-up circuit, a bias current generator, and a voltage subtraction output stage. Fabricated in a 0.18 µm CMOS process, the circuit achieves a power consumption of 17 nW at 27 °C with a supply voltage ranging from 1 to 3 V. At <i>V</i><sub>DD</sub> = 1.8 V, the output reference voltage (<i>V</i><sub>REF</sub>) is 297.3 mV, exhibiting a temperature coefficient (TC) of 2.565 ppm/°C over a temperature range of from − 40 to 125 °C. The power supply ripple rejection ratio (PSRR) at 10 Hz is − 102.9 dB. The proposed architecture demonstrates advantages in low-power consumption, compact area, and stable output performance.</p></div>\",\"PeriodicalId\":7827,\"journal\":{\"name\":\"Analog Integrated Circuits and Signal Processing\",\"volume\":\"124 1\",\"pages\":\"\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Analog Integrated Circuits and Signal Processing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://link.springer.com/article/10.1007/s10470-025-02421-0\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q4\",\"JCRName\":\"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Analog Integrated Circuits and Signal Processing","FirstCategoryId":"5","ListUrlMain":"https://link.springer.com/article/10.1007/s10470-025-02421-0","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q4","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
A subthreshold CMOS voltage reference with low temperature coefficient, low power and high PSRR
This paper proposes a subthreshold CMOS voltage reference circuit. The design comprises a start-up circuit, a bias current generator, and a voltage subtraction output stage. Fabricated in a 0.18 µm CMOS process, the circuit achieves a power consumption of 17 nW at 27 °C with a supply voltage ranging from 1 to 3 V. At VDD = 1.8 V, the output reference voltage (VREF) is 297.3 mV, exhibiting a temperature coefficient (TC) of 2.565 ppm/°C over a temperature range of from − 40 to 125 °C. The power supply ripple rejection ratio (PSRR) at 10 Hz is − 102.9 dB. The proposed architecture demonstrates advantages in low-power consumption, compact area, and stable output performance.
期刊介绍:
Analog Integrated Circuits and Signal Processing is an archival peer reviewed journal dedicated to the design and application of analog, radio frequency (RF), and mixed signal integrated circuits (ICs) as well as signal processing circuits and systems. It features both new research results and tutorial views and reflects the large volume of cutting-edge research activity in the worldwide field today.
A partial list of topics includes analog and mixed signal interface circuits and systems; analog and RFIC design; data converters; active-RC, switched-capacitor, and continuous-time integrated filters; mixed analog/digital VLSI systems; wireless radio transceivers; clock and data recovery circuits; and high speed optoelectronic circuits and systems.