Investigation of electrical parameters in extended source epitaxial layer DG-TFET including interface trap charges and temperatures

Abstract

In this work, we have highlighted the electrical parameters of extended source epitaxial layer double gate TFET (ESETL-DGTFET) for the wide variation in temperatures and interface trap charge density. The DC, RF/analog, and linearity behaviour are reported for variation in positive interface trap charge (PITC)/ negative interface trap charge (NITC) along with wide temperature variations (250–400) K using TCAD simulator. It is seen that PITC improved the electrical parameters like current ratio, cut-off frequency, linearity behaviour, whereas, NITC degrades the same. The degradation in OFF state current at low gate bias with increased temperature is due SRH rate is exponentially dependent on temperature, whereas, band to band tunnelling (BTBT) rate is weak dependence of temperature leads to negligible variation in drain current at high gate bias. With increased temperature, the current ratio degrades and delay improved for both PITC and NITC. The temperature sensitivity is improved in presence of PITC compared to NITC.