A high speed-low power compressor with novel structure for reducing the complexity of wallace multipliers

Abstract

Nowadays power, delay in addition to the area has to turn out to be the attribute features of any VLSI circuit. Usually, the delay of usual multipliers is high due to the number of computations, consequently; the overall speed of circuits become less, and increases power consumption. The performance of Digital Signal Processing (DSP) processors is frequently dependent on the Multiplier and Accumulator (MAC) unit, and three parameters determine it, namely power, area and speed. However, the performance of the conventional MAC is not good when the number of bits increases and also using several multiplication factors increases the power consumption. So, to reduce the compressor size for working with a higher level of bits in lower power and low area consumption, this paper proposes a new architecture for an effective MAC unit. In the proposed architecture, the Peres logic gates are applied in the third compression stage for reducing the power compression and delay. The outcomes demonstrate that the suggested design has high speed and low MAC unit area consumption. Furthermore, the increase in the compressor size is not affecting the system operations. The proposed architecture can be applied for future DSP system to get efficient performance.