Majority voting for low power and low complexity preamble detection by hybrid memristor-CMOS architecture

Abstract

In modern embedded systems, efficient and low-power communication is essential, especially as these systems increasingly handle concurrent wireless protocols. Preamble detection is a critical step in synchronizing received signals after demodulation, yet traditional methods—such as correlation and Hamming distance techniques—suffer from high power consumption and computational complexity. To address these challenges, this paper proposes a novel majority voting-based pattern recognition method that enhances detection accuracy while reducing energy consumption. By leveraging majority voting, our approach mitigates noise effects and improves signal robustness, enabling more efficient preamble detection across varying signal-to-noise ratios (SNRs). The proposed method is implemented in both CMOS-based and hybrid memristor-CMOS architectures, where the hybrid design incorporates dedicated complementary circuits to further optimize power efficiency and reduce silicon area utilization. Unlike conventional CMOS-only implementations, our hybrid approach reduces redundant computations and enhances energy efficiency, making it well-suited for resource-constrained applications. Performance evaluation demonstrates significant improvements over existing techniques, highlighting the potential of memristor-CMOS hybrid technology in low-power, high-speed communication systems.