Performance improvement in asynchronous binary search ADC using bootstrapped sample and hold circuit & 2-stage ladder network

Abstract

This paper presents a design of an 8-bit asynchronous, binary search analog-to-digital converter (ADC) using an asynchronously generated clock signal and inbuilt Bootstrapped sample and hold circuit by utilizing a 2-stage ladder for generation of reference voltages. The proposed design utilizes an anti-aliasing filter and Bootstrapped sample and hold circuit for charge cancellation with only N comparators, \(2^{(N-3)}\) multiplexers, and a switching network. The ADC achieves an SNR of 47.4 dB, an ENOB of 7.7 bits, \(\text {f}_{in}\) of 200 KHz, \(\text {f}_{s}\) of 125 MSPS, and dissipates 13 mW of power when operated on 1.8 V supply rail. The proposed design had resulted in saving 10\(\%\) of chip area with respect to a recent candidate SAR ADC and more than 50\(\%\) of chip area with respect to flash ADC. The proposed design also showed 61.7\(\%\) improvement in speed with respect to existing SAR architectures due to switching networks. Pre and post-layout simulation results showed a conversion time of approximately 5.2 ns and 6.5 ns respectively, while Monte Carlo simulation and process corner analysis showed good results with less spread. Further, the static characteristics that have been plotted for resistor mismatch showed linearity approximation in the nominal range. The design has the merit of being that choice for radio frequency identification applications.