2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献_第6页

Development of wafer level solderball placement process for RDL-first FOWLP RDL-first FOWLP晶圆级焊球放置工艺的开发

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315079

S. Lim, N. Jaafar, S. Chong, S. Lim, T. Chai

{"title":"Development of wafer level solderball placement process for RDL-first FOWLP","authors":"S. Lim, N. Jaafar, S. Chong, S. Lim, T. Chai","doi":"10.1109/EPTC50525.2020.9315079","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315079","url":null,"abstract":"The Fan-out wafer-level packaging technology is an integrated circuit technology as well as an enhancement of standard wafer-level packaging (WLP) solutions. This technology is an attractive packaging approach for mobile applications and heterogeneous integration. It allows better electrical performance, low form factor and at relatively low cost as compared to wafer to wafer stacking or 3D stacked bonding. Furthermore, as the industry moving towards higher density and higher-bandwidth chip to chip interconnections, the application of Package on Package technology offers a solution for applications processors and mobile applications with better thermal and electrical performance. One of the significant advantages of package-on-package FOWLP is the ability of stacking 2 different packages to achieve multi-functionality. However, the overall package has to maintain a low profile for thin portable applications. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is after singulation. The work in this paper focus on the development and process of wafer level solderball placement on a molded wafer using RDL-first FOWLP process. The Fanout molded wafer is 0.47mm thick and the package size is $15 times 15 mathbf{mm}^{2}$ after singulation. Detailed process parameters on flux printing process parameters such as the printing speed and printing gap coupled with ball placement speed, ball dispense gap and ball head moving direction needs to be evaluated to achieve robust wafer level solderball placement process with good flux printing and good ball placement process yield.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"467 1","pages":"435-439"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86717146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Study on Cu Wire Wedge Crack and Fatigue Life Prediction during Thermal Cycling Test (TCT) 热循环试验(TCT)中铜丝楔裂及疲劳寿命预测研究

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315045

Billie Xianghong Bi, H. Fan, Jun Yang, Haibin Chen

{"title":"Study on Cu Wire Wedge Crack and Fatigue Life Prediction during Thermal Cycling Test (TCT)","authors":"Billie Xianghong Bi, H. Fan, Jun Yang, Haibin Chen","doi":"10.1109/EPTC50525.2020.9315045","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315045","url":null,"abstract":"It is widely believed that wedge crack is resulted from thermal stress occurring at wire bonding area due to coefficient of thermal expansion (CTE) mismatches among epoxy molding compound (EMC), Cu wire, and Leadframe, and wedge bond heel area has the highest risk due to higher stress concentration. To fully understand the wedge crack failure mechanism and the way to improve its fatigue life, in this study, the wedge bond performance under TCT was evaluated in a small outline transistor package with different wire bonding settings, different types of EMC with different CTEs and modulus. The results showed that the TCT performance of Cu wire wedge bond depended on the wire bonding setting, CTE of EMC, adhesion between EMC and Leadframe, wire diameter, etc. Through suitable material selection, package design, process optimization, Cu wire wedge crack during TCT can be avoided to achieve the increasingly higher reliability requirement. Furthermore, numerical modeling was developed to predict Cu wire wedge bond fatigue life with those different factors during TCT. For given packages, modelling can provide a comparison on accumulative plastic strain ($Deltavarepsilon_{mathrm{p}}$) at Cu wedge bond to identify the effect of factors on Cu wedge fatigue crack. Fatigue parameters can be derived by simulation results and experimental data. Regarding to these fatigue parameters, TCT fatigue life can be predicted for a given package.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"44 1","pages":"168-171"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86132412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Material Removal Rate Prediction using the Classification-Regression Approach 分类回归方法的材料去除率预测

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315140

Kart-Leong Lim, R. Dutta

引用次数: 2

Wafer Level Fine-Pitch Hybrid Bonding: Challenges and Remedies 晶圆级细间距杂化键合:挑战与补救

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315002

V. Chidambaram, Yew Wing Leong, Qin Ren

引用次数: 5

High performances 3D heterogeneous integrated devices based on 3D silicon capacitive interposer 基于三维硅电容中间体的高性能三维异构集成器件

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315000

M. Jatlaoui, C. Muller

引用次数: 3

Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging 芯片封装中逻辑对逻辑和HBM互连模型信号完整性性能评估的频域方法

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315036

Li Kangrong, M. D. Rotaru

{"title":"Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging","authors":"Li Kangrong, M. D. Rotaru","doi":"10.1109/EPTC50525.2020.9315036","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315036","url":null,"abstract":"A novel methodology to evaluate the signal integrity (SI) performance of logic to logic and high bandwidth memory (HBM) interconnect model for chiplet packaging is proposed. Compared with the traditional S parameters and eye diagram analyses, the proposed methodology reflects the actual SI performance under the capacitive termination condition, takes much shorter simulation time and provides more insightful SI evaluation, which is suitable for logic to logic and HBM interconnect design and optimization. The S parameters analysis are not sufficient for the cases like logic to logic and HBM interconnect models, which are unterminated (capacitive loading). The eye diagram analysis cannot provide an insightful guideline for optimization of interconnect model. Besides, eye diagram simulations to find the optimum interconnect model are very time consuming, as a frequency domain to time domain via an inverse fast Fourier transformation (FFT) is required. Compared with the eye diagram analysis, the proposed methodology only analyses the SI performance in frequency domain rather than in time domain, so the simulation time is reduced. The proposed methodology can overcome the drawbacks of the S parameters and eye diagram analyses and provide an in-depth and fast evaluation on the SI performance of logic to logic and HBM interconnect models frequently encountered in advanced system in package using chiplets.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"100 1","pages":"147-151"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84267022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dry Etched Through SiC Via (TSiCV) Process Analysis Using DOE Modeling 基于DOE模型的干蚀刻SiC通孔工艺分析

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315121

P. Mackowiak, M. Schiffer, Martin Scheider-Ramelow, K. Lang

引用次数: 0

Built-in Stress effects of IC package substrate's layers on its warpage at room temperature 室温下IC封装基板层内建应力对其翘曲的影响

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315057

Min-Sung Kim, H. Jung, Sunghyun Park, Tae-Hyung Kim, E. Ahn, Young-Hwan

引用次数: 0

Non-destructive fault isolation in through-silicon interposer based system in package 封装中基于通硅中间层的系统的无损故障隔离

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315038

Sajay Bhuvanendran Nair Gourikutty, Kok Keng Chua, J. Alton, Jong Ming Chinq, Ratan Bhimrao Umralkar, V. Chidambaram, S. Bhattacharya

引用次数: 2

Thermomechanical Stress and Strain Distribution and Thermal Resistivity Correlation to Bondline Thickness of Ag Sinter 银烧结矿的热机械应力应变分布及热电阻率与结合线厚度的关系

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315142

Bobby Johns L. Villacarlos, Marty Lorgino D. Pulutan

{"title":"Thermomechanical Stress and Strain Distribution and Thermal Resistivity Correlation to Bondline Thickness of Ag Sinter","authors":"Bobby Johns L. Villacarlos, Marty Lorgino D. Pulutan","doi":"10.1109/EPTC50525.2020.9315142","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315142","url":null,"abstract":"Stress and strain energy distribution and thermal resistivity of diebonded Si dies were measured and correlated with varying bondline thickness of hybrid Ag sinter to define and optimize workable bondline thickness window. Thermomechanical simulations were done using carrier device with known PPF-plated Cu flange, Si die, epoxy mold compound and Ag sinter material properties. Principal stress, total strain energy density and interfacial stress distribution were obtained to check susceptibility to die crack, cohesive and adhesive failure respectively using Finite Element Analysis. On the other hand, thermal resistivity (Rth) per die section (Final Peak, Final Carrier, Driver Peak, and Driver Carrier) were measured across varying dry bondline thickness of 20, 40 and $60mu mathrm{m}$. Results reveal that maximum principal stress, strain energy and interfacial stress experienced on the die, die-attach, and die backside - die-attach interface are inversely proportional to the bondline thickness of Ag sinter which means lower bondline thickness are more susceptible to reliability failures. Moreover, thermal resistivity on all die sections dramatically increases with increasing bondline thickness and should be controlled within 20 to $60mu mathrm{m}$ thickness range.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"307-311"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82856451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6