Built-in Stress effects of IC package substrate's layers on its warpage at room temperature

Abstract

This paper presents that built-in stress of copper, FRP and solder-resist (SR) layers is critical to predict an IC package substrate's warpage at room temperature. The built-in stresses are 78MPa on copper, 16MPa on FR4 and 9MPa on SR through simple bilayer's curvature and strain-curvature analytic model. Specifically, the built-in stress of copper layers has distinct value depending on circuit process; that is, average built-in stress of 78, 136 and 53MPa are loaded on the copper layer of tenting, MSAP, and PSAP respectively. Besides, in curing process, uncured FRP has a material-dependent built-in stress, namely 22 and 15MPa on each type D and E of FRP. Moreover, SR also has built-in stress, 6 and 23MPa on each type A and B of SR. It is shown that simulation results considered built-in stress are in good agreement with measured warpage of simple bilayer substrate. To conclude, it is verified that built-in stress of copper, FRP, and SR affects warpage of IC package substrate at room temperature.