2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献

Establishing the Single-Phase Cooling Limit for Liquid-Cooled High Performance Electronic Devices 建立液冷高性能电子器件的单相冷却极限

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315014

G. Refai-Ahmed, Hoa Do, Yaser Hadad, S. Rangarajan, B. Sammakia, V. Gektin, T. Cader

{"title":"Establishing the Single-Phase Cooling Limit for Liquid-Cooled High Performance Electronic Devices","authors":"G. Refai-Ahmed, Hoa Do, Yaser Hadad, S. Rangarajan, B. Sammakia, V. Gektin, T. Cader","doi":"10.1109/EPTC50525.2020.9315014","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315014","url":null,"abstract":"The objective of this paper is to establish the cooling limit for forced single-phase liquid-cooling of high performance electronic devices such as CPUs, FPGAs and GPUs. This limit is established based on the design and optimization of a liquid-cooled copper cold plate populated with microchannels, which is used to cool a single chip with uniform heat flux. A shape optimization strategy based on the RSM (response surface method) was used to minimize pressure drop and maximum chip case temperature. The effects of the fin thickness and channel spacing were captured by the numerical simulation. The optimization was performed for constant values of coolant flow rate and chip power. The influence of fin geometry, channel geometry total heat transfer surface area on the hydraulic and thermal performance of the heat sink was determined using CFD (computational fluid dynamics) simulations at RSM design points. The optimum designs were achieved by minimizing a weighted objective function defined based on response parameters using the JAYA algorithm. Finally, a parametric study was performed to establish the thermal limit of the single-phase liquid-cooled heat sink within a constrained pressure drop of 10kPa. The best-performing heat sink shows a resistance 0.15 °C cm2/W (based on chip area of 4cm2). The current proposed liquid-cooled heat sink can handle close to 170W/cm2 at a thermal budget of 50°C from chip to the ambient under controlled pressure drop of less than 10 kPa.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"340-346"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74257669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Investigation of Thermal Performance of Antenna in Package for Automotive Radar System 汽车雷达系统封装天线热性能研究

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9314988

Yong Han, T. Chai, T. Lim

引用次数: 2

Solder Joint Reliability of Double sided Assembled PLP Package 双面组装PLP封装的焊点可靠性

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315097

J. Ha, Yeonseop Yu, Kang-Young Cho

引用次数: 1

Impact of Process Variations on the Capacitance and Electrical Resistance down to $1.44 mumathrm{m}$ Hybrid Bonding Interconnects 工艺变化对$1.44 mumath {m}$混合键合互连电容和电阻的影响

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315028

B. Ayoub, S. Lhostis, S. Moreau, E. L. Pérez, J. Jourdon, P. Lamontagne, E. Deloffre, S. Mermoz, C. de Buttet, V. Balan, C. Euvard, Y. Exbrayat, H. Frémont

{"title":"Impact of Process Variations on the Capacitance and Electrical Resistance down to $1.44 mumathrm{m}$ Hybrid Bonding Interconnects","authors":"B. Ayoub, S. Lhostis, S. Moreau, E. L. Pérez, J. Jourdon, P. Lamontagne, E. Deloffre, S. Mermoz, C. de Buttet, V. Balan, C. Euvard, Y. Exbrayat, H. Frémont","doi":"10.1109/EPTC50525.2020.9315028","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315028","url":null,"abstract":"With the rising of Hybrid Bonding (HB) as an interesting solution for fine-pitch 3D integration, the influence of process induced variations on performances is a demanding and crucial task. A 3D stacked test vehicle with hybrid bonding pitch ranging from 6.8 down to $1.44 mu mathrm{m}$ was processed and analyzed. A deep analysis on the influence of process variations is conducted and correlated to electrical measurements thanks to a dedicated simulation methodology. This allows a better understating of the process variation parameters that affects electrical resistance and capacitance along with their relative importance which is essential for optimization. The common parameter affecting both capacitance and electrical resistance is Wafer-to-Wafer overlay between top and bottom wafers arising the need for high accuracy in bonding alignment. The quality of the hybrid bonding interface is discussed thanks to the simulation model, before and after robustness tests depending on hybrid bonding pitch, leading to an estimation of contact resistivity around $2. 10^{-10}Omega.cm^{2}$ for the $1.44 mu mathrm{m}$-pitch structure.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"56 1","pages":"453-458"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89096874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Fast Finite Element Modeling Method for TSV Interposer on Specially Developed SAAS Cloud 基于SAAS云的TSV中介器快速有限元建模方法

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315110

Xiaodong Wu, Shengli Ma

{"title":"Fast Finite Element Modeling Method for TSV Interposer on Specially Developed SAAS Cloud","authors":"Xiaodong Wu, Shengli Ma","doi":"10.1109/EPTC50525.2020.9315110","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315110","url":null,"abstract":"The coupled thermo-mechanical field analysis of TSV interposer is a typical multiscale simulation problem, it faces great difficulty of numerous TSVs and complex micro structures. To get balance between accuracy and efficiency, global/local finite element (GLFE) strategy often be used in the multiscale coupled field analysis. In steps of the GLFE strategy, global coarse mesh evaluation plays the key role and the mesh model of this step determines the calculation effect. Currently, finite element modeling for TSV interposer is mostly finished manually with the help of comprehensive finite element software. To improve the laboriously and time-consuming manual modeling procedures, a finite element modeling method specifically oriented for TSV interposer is proposed. The modeling method is an imitation of fabrication procedures, it consists of layer based geometry modeling, parametric meshing, automatic contact detection, automatic boundary condition building and automatic loading processes. TSV discretization methods affected the quality of the mesh model directly, 4 kinds of TSV discretization methods are proposed in this paper, namely: Fine Mesh Method, Single Point Method, Single Mesh Method and Equivalent Model Method, they reach different equilibrium points on model size and accuracy, feeding need of different simulation scenarios. As the implementation of the modeling method a SAAS cloud system is built, the system run in B/S mode and it can make the modeling procedures easier. Finally, with the help of the modeling method and the SAAS cloud system, a thermo-mechanical analysis of TSV interposer based 2.5D RF module is done. The comparison of the time consumption and results with comprehensive finite element software ANSYS Workbench indicates that the cloud system can get great efficiency with enough accuracy.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"273-280"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84763128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Direct Patterning of Conductive Fine Line in Dielectric Layer for Semiconductor Package 半导体封装介质层导电细线的直接图像化

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315133

Jung Shin Lee, Jung-Woo Cho, S. Park, Seungdon Lee, Hyun-Yong Lee, Daniel Min Woo Rhee

{"title":"Direct Patterning of Conductive Fine Line in Dielectric Layer for Semiconductor Package","authors":"Jung Shin Lee, Jung-Woo Cho, S. Park, Seungdon Lee, Hyun-Yong Lee, Daniel Min Woo Rhee","doi":"10.1109/EPTC50525.2020.9315133","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315133","url":null,"abstract":"Using inkjet printing, fine conductive lines could be obtained through a combination of suitable substrate wettability. we performed study on what surface conditions are necessary to form a well-defined line using MOD ink. We searched for a combination of wettability to achieve the target line width through numerical analysis. Lattice Boltzmann method (LBM) was used for the numerical technique. The behavior of micro droplets moving on the wettability contrast was analyzed. In addition, the evaporation of water droplet is considered in current study. The behavior of the ink droplet was observed according to the contact angle of the substrate and wetting band. Effect of non-uniform wettability also discussed. And finally, based on the information obtained from numerical analysis, we applied it to the experiment to make fine conductive lines. Contact angle of substrate should not be super-oleophobic, where the evaporation effect is small. And if oleophilic, since the overshoot of the droplet width was large, the wettability of the substrate should be moderate. On the other hand, to obtain driving force through oleophilicity, the wetting band must have high oleophilicity. In the experiment, MOD ink was deposited to specimen to make conductive line $5mumathrm{m}$ and $8mumathrm{m}$ widths.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"472-478"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88631277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of a laser-assisted bonding process for a flip-chip die with backside metallization 背面金属化倒装芯片的激光辅助键合工艺研究

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315012

Wagno Alves Braganca, Kim KyungOe, Kim YoungCheol

引用次数: 3

Fan-Out Wafer Level Packaging Development Line 扇形圆片级封装开发线

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315155

Chai Tc, D. Ho, Chong Sc, Hsiao Hy, Serine Soh, S. Lim, S. Ps, E. Wai, Lau Bl, Seit Ww, Lau Gk, Phua Ts, K.C.S. Lim, S. Sh, Ye Yl

{"title":"Fan-Out Wafer Level Packaging Development Line","authors":"Chai Tc, D. Ho, Chong Sc, Hsiao Hy, Serine Soh, S. Lim, S. Ps, E. Wai, Lau Bl, Seit Ww, Lau Gk, Phua Ts, K.C.S. Lim, S. Sh, Ye Yl","doi":"10.1109/EPTC50525.2020.9315155","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315155","url":null,"abstract":"With the slowing down of Moore's law, the semiconductor industry is increasingly looking to advanced packaging for achieving system scaling at packaging level. Across the industry, in high volume factories that support assembly and packaging of semiconductor ICs, fabless companies, foundries, equipment and materials developers, increased constraints are seen in terms of allocating resources for research and development of advanced packaging technologies and solutions to meet market requirements. IME has worked with multiple industry partners to establish a FOWLP development Line to address these challenges to build broad advanced-packaging platforms to enable product and technology pathfinding for industry applications such as mobility, 5G, mmWave, Data Centre and automotive requirements This paper will provide an overview of the FOWLP development line, review of mold 1st and RDL 1st FOWLP technologies with multi-layer 2um line and spacing, RDL process and integration on 300mm wafer. The example of few novel packaging approaches such as large size RDL molded interposer with and without embedded fine interconnect chip, 3D integrated package-on-package, and the 2-layer molded antenna-in-package will be described.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"151 1","pages":"440-444"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79556070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Development of RDL-1stFan-Out Panel-Level Packaging (FO-PLP) on $550text{mm}times 650text{mm}$ size panels 在$550text{mm} × 650text{mm}$尺寸的面板上开发RDL-1stFan-Out面板级封装(o - plp)

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315163

S. Chong, V. S. Rao, Kazunori Yamamoto, Sharon Lim Seow Huang

引用次数: 1

Establishing Thermal Air-cooled Limit for High Performance Electronics Devices 建立高性能电子器件的热风冷极限

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315139

G. Refai-Ahmed, Hoa Do, Yaser Hadad, S. Rangarajan, B. Sammakia, V. Gektin, T. Cader

{"title":"Establishing Thermal Air-cooled Limit for High Performance Electronics Devices","authors":"G. Refai-Ahmed, Hoa Do, Yaser Hadad, S. Rangarajan, B. Sammakia, V. Gektin, T. Cader","doi":"10.1109/EPTC50525.2020.9315139","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315139","url":null,"abstract":"This manuscript explores the design and optimization of an air-cooled heat sink and establishes thermal performance limits for the air-cooling of high power electronic devices. The air-cooling limit is established based on a numerical model. This model correlates the thermal performance of an FPGA with the test data from a standalone active VCK5000 PCIe card. Using Ansys Icepak V19.1 software, a series of CFD (computational fluid dynamics) simulations is performed with an FPGA power level of 1,000W, which is recently discussed in different roadmap such as HIR [1]. The purpose of the CFD model is to determine the temperature and flow fields over a range of airflow rates, and to develop a correlation for the convective thermal resistance, as a function of the flow parameters. A heat sink shape optimization is performed by simple Brute force in order to minimize the pressure drop and die maximum case temperature. The effects of the heat sink's fin thickness and channel spacing are analyzed numerically. The optimization is performed for the constant values of air velocity and chip power. The optimized air-cooled heat sink with a vapor chamber base using a thermal interface material (TIM) with an effective thermal conductivity of 20W/mK and effective thickness of 70um is shown to able to operate at a heat flux 45-55W/cm2 for either 1U or 4U server, while still meeting max allowable FPGA operating case temperature.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"347-354"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75732127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6