Development of RDL-1stFan-Out Panel-Level Packaging (FO-PLP) on $550\text{mm}\times 650\text{mm}$ size panels

Abstract

Industry is constantly looking at ways to reduce the cost of manufacturing. One of the common cost reduction methods is to increase the size of the substrate. The wafer size was increased previously from 6″ to 8″ and then from 8″ to 12″ to increase the number of dies per wafer. The increase in die population per wafer improves the throughput of the processes and hence, reduces the manufacturing cost. Industry is looking towards moving from round wafer to square or rectangle panel in order to further increase the number of dies per substrate. The panel size evaluated in this work is of dimension. The die size usedis with up to 4000 solder bumps. We have developed the RDL 1st Fab-Out Panel-Level Packaging on size panel. The panel size evaluated in this work is of $550\text{mm}\times 650\text{mm}$ dimension. The die size usedis $10\text{mm}\times 10\text{mm}\times 0.7\text{mm}$ with up to 4000 solder bumps. We have developed the RDL 1st Fab-Out Panel-Level Packaging on $550\text{mm}\times 650\text{mm}$ size panel.