2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Epoxy Molding Compound Development for Improved MSL1 Delamination Resistance in Plastic Encapsulated Clip Bond Power Package","authors":"April Joy H. Garete, Zhiwen Li, Arnel Taduran","doi":"10.1109/EPTC50525.2020.9315114","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315114","url":null,"abstract":"Package delamination after reflow is a critical failure attribute for power electronic devices. Delamination reduces the path for removing the heat generated by the device and severely affects its functionality. Major factors affecting delamination in clip bonded devices include the moisture absorption of epoxy molding compound (EMC) and induced thermomechanical stresses in the package. In this study, four advanced formulation EMCs developed to improve delamination resistance of a clip bond power package were evaluated. These EMCs were formulated to the have low moisture absorption as well as low modulus. This was achieved using multi-aromatic resins, low moisture absorption hardeners and increased filler content (>80wt%). To determine the moisture absorption characteristic of the materials, these were subjected to moisture sensitivity level 1 (MSL1) conditions and 3x reflow at 260°C. Preconditioning was performed to simulate the stress that the package would experience during PCB assembly. The amount of moisture absorbed and moisture diffusion coefficient of the EMC after saturation were determined using weight gain experiments. Thermal analysis was done to determine coefficients of thermal expansion, glass transition temperature and elastic modulus of the EMCs. The stress induced by the EMC on die and leadframe interfaces were calculated based on the material property characterization results. Amount of delamination before and after reflow simulation was measured and analyzed using Scanning Acoustic Microscopy. Overall results showed that low moisture absorbing (<0.3wt%) molding compounds performed best. Lower stress index at reflow process conditions were also obtained with lower CTE mismatch to Si and Cu, low Tg (<150°C) and low modulus at high temperature (<0.74 GPa). Zero delamination was achieved on Si die interface while the delamination on Cu leadframe interface after MSL1 preconditioning significantly improved with low stress EMC properties. Excellent combination of mold compound material properties enabled a plastic encapsulated power clip bond package to achieve improved MSL1 delamination resistance towards more robust power electronics packaging.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"90-94"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74340609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Aging and Ball Shear Characterization of SAC-X Solders for Wafer Level Packaging","authors":"N. Jaafar, C. Choong, Sharon Lim Pei Siang, C. T. Chong","doi":"10.1109/EPTC50525.2020.9315175","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315175","url":null,"abstract":"Current industry trends in the microelectronics packaging is going towards increasing in I/O density and small size packaging. Common use of solder material in packaging are the lead free solders. The popular lead free alloys include the SnAgCu (SAC) family such as SAC 305 and SC405. SAC solder alloys are favor due to high stains rate transient load and reliable operation at high temperature. Hence, it is suitable for application such as military application, avionics, and automotive [1], [2]. SAC alloy is frequently used in Wafer Level Chip Scale Package designs but achieving board level reliability especially when footprint go beyond a certain size causes challenge for SAC solder ball [3]. To overcome this issues, new type of solder alloy, SACQ and QSAC, has been established in current market to improve board level reliability performance. In this paper, studies of the 2nd level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work. In this paper, studies of the 2nd level solder joint of the SAC305, SAC-Q and QSAC solder ball in terms of ball shear strength measurement at time zero and its failure mode will be shared. The SAC305, SACQ and QSAC solder alloys are also subjected to High Temperature storage (HTS) at 150°C for up to 1000hrs. The different IMC layers and the IMC growth will be investigated in this work.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"64 1","pages":"321-325"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79283347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Laser drilling and Plasma Cleaning Process for Blind Via Through Mold Interconnect","authors":"H. Hsiao, David Soon Wee Ho, Keith Cheng Sing Lim, S. Chong, T. Chai, David Schutzberger, Yariv Oz, Guy Amrani, Jack Q. Zhao, Johnson Toh","doi":"10.1109/EPTC50525.2020.9315051","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315051","url":null,"abstract":"Through Mold Interconnects (TMI) process is currently mainly used in advanced packaging processes. In this research, laser drilling technology is used to fabricate TMI on epoxy mold compound materials with different filling sizes and plasma is used to clean the epoxy residues after laser drilling. The micro-second ultraviolet (UV) laser is used for laser drilling. A punch mode is used to drill blind vias, and different laser beam sizes, fluence and number of pulses were adjusted to achieve blind vias with an aspect ratio of 1:1. The plasma cleaning using CF4/O2 gas chemistry after laser drilling is to use to clean the residual material on the surface of the blind vias.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"14-18"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82174536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Yield Improvement of Silicon Trench Isolation for One-Step TSV","authors":"Xiangy-Yu Wang, Qin Ren, M. Kawano","doi":"10.1109/EPTC50525.2020.9315080","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315080","url":null,"abstract":"Three-dimensional (3D) integration via wafer stacking can provide another option for the Moore's law when the channel length of a transistor is coming to a limit of atomic scale physical dimension. There are many approaches to realize vertical interconnection between double stacked wafers. One of innovative methods is one-step TSV, which enables TSV process to be more cost effective comparing with the conventional TSV fabrication [1]. Fig. 1(a) shows a conventional TSV scheme to connect the two memory wafers and Fig. 1(b) is the new developed approach to connect the two memory wafers by a one-step TSV with the silicon-trench isolation. In this study, we will discuss about the issues that we encountered during this silicon-trench fabrication and how we overcome and improved them by optimizing the process and adding in some necessary inline monitor.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"25 1","pages":"22-26"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84393586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of Pressure Sensing Array System for Retail Inventory Management","authors":"Ruiqi Lim, D. Choong, Ming-Yuan Cheng","doi":"10.1109/EPTC50525.2020.9315015","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315015","url":null,"abstract":"There have been various challenges associated with inventory management for supermarkets. These includes labor intensive stock taking procedures and mismatching of goods in retail store as compared to system record. These challenges will eventually result in the loss of sale for the company. In order to address the mismatching of goods and labor intensive issue, there is a need for real-time monitoring of the goods on the retail shelves. These will reduce the needs for manual stock taking, improve the efficiency in goods replenishment and thus resulting in overall sale profit. In this work, $8 times 8$ pressure sensing array substrate with wireless module readout and tablet application has been developed as a demonstration prototype for monitoring the weight of goods on the shelve. The sensing system achieved a average repeatability error of 5.3% for a force range of 0.2N to 10.2N via bench-top charcaterisation setup. System firmware algorthim has been validated with a data error of less than 3% as compared to theoretical calculation.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"185-188"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82839034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fabrication of vertical through-holes to realize high throughput cell counting","authors":"Yu Chen, Ming-Yuan Chen","doi":"10.1109/EPTC50525.2020.9315101","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315101","url":null,"abstract":"It is desirable to have high throughput cells counting and sizing for various biomedical applications. We have previously reported a micro-machined multiple-channel Coulter counter device to realize such a requirement at a low cost. To further extend the throughput of the device, a 2-D array needs to be developed, and each microchannel (vertical through-hole) should have an independent fluidic pass. In this paper, we present the process flow to fabricate the vertical through-hole array chip. The whole fabrication process is CMOS (Complementary metal-oxide-semiconductor) compatible. The enhanced throughput and sensitivity have been demonstrated by measuring various sized cells in a buffer solution.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"56 1","pages":"189-193"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88544308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thin-Film Magnetic Inductor Design Strategy for Integrated Voltage Regulator","authors":"S. Raju, Narasimman Neelakantan, Serine Soh, D. Ho, R. Singh","doi":"10.1109/EPTC50525.2020.9315027","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315027","url":null,"abstract":"The optimal design of thin-film magnetic inductor is important to realize efficient fully Integrated Voltage Regulators (IVR). This work describes the origin of the power losses within inductor while switching at high frequency, and proposes an inductor selection strategy that is able to maximize efficiency for a desired operating condition. The optimization strategy was employed to design an inductor for IVR application which is switching at 50 MHz. To show the effectiveness of the proposed strategy, the thin-film magnetic inductor was fabricated and integrated with CMOS ASIC to realize an 8-phase IVR that yielded a peak efficiency of 85% over a wide load range of 1.5 A.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"21 5 1","pages":"159-161"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89389477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of Paramagnetic Defects in SiCN and SiCO-based Wafer Bonding","authors":"L. Peng, S.-W. Kim, S. Iacovo, J. de Vos, B. Schoenaers, A. Stesmans, V. Afanas'ev, A. Miller, G. Beyer, E. Beyne","doi":"10.1109/EPTC50525.2020.9315054","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315054","url":null,"abstract":"We present fundamental exploration of inorganic dielectric wafer-to-wafer (W2W) bonding by electron spin resonance (ESR) to assess the function of dangling bond-type interface defects. As compared to a standard PECVD SiO2 which contains negligible dangling bonds (DBs), it is found that a substantial amount of silicon and carbon types of DBs, as high as 1014 cm-2, are present in the pre-bonding layer of SiCN and SiCO, mainly as a result of surface modification by means of low energy plasma activation prior to bonding. It is inferred that the evolution of DBs has a positive influence on improving the wafer bonding energy during post-bond anneal, in that the results suggest that a decrease of DBs translates into the formation of chemical bonds at the bonding interface.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"225 1","pages":"464-467"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80097058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modelling and prediction on process dependent wafer warpage for FOWLP technology using finite element analysis and statistical approach","authors":"L. Ji, T. Chai, G. See, P. Suo","doi":"10.1109/EPTC50525.2020.9315147","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315147","url":null,"abstract":"A Finite Element Analysis (FEA) modelling on process dependent wafer warpage for Fan Out Wafer Level Packaging (FOWLP) technology is presented in this paper. Instead of using conventional Design-of-Experiment (DOE) approach, the numerical parametric study is performed based on the DOE table generated by statistical data analysis tool. By analyzing the modelling results, the statistical tool is able to derive the wafer warpage prediction equations for each process steps. For any parameters within the data ranges prescribed in DOE table, wafer warpage can be quickly calculated by using the prediction equations. Case study on wafer warpage for two high density package designs for different FOWLP process steps is presented. Critical parameters that impact wafer warpage significantly are identified for each process step by the statistical tool. This established methodology is able to predict wafer level warpage for FOWLP processes efficiently so that the design and process parameters could be co-optimized to address the wafer warpage issues.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"55 1","pages":"386-393"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88503769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal characterization of SiC MOSFETs for automotive power module","authors":"Jung Kyun Kim","doi":"10.1109/EPTC50525.2020.9315151","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315151","url":null,"abstract":"This paper shows that thermal characterization of SiC MOSFETs for automotive power module using the thermal transient measurement method, simulation, calibration, and boundary condition independent reduced order model. Thermal transient measurement method was used to determine the thermal resistance of the junction to case. As a second task, the thermal model calibration using the thermal transient measurement was built for even more accurate thermal simulations and improve the reliability of components. We also demonstrated the boundary condition independent reduce order model (BCI-ROM) for automotive mission power profile from a full detailed calibrated model. Model order reduction aims to lower the computational complexity thus allowing for faster solving while maintain predictive accuracy in space and time.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"335-339"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85616999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}