Yield Improvement of Silicon Trench Isolation for One-Step TSV

Abstract

Three-dimensional (3D) integration via wafer stacking can provide another option for the Moore's law when the channel length of a transistor is coming to a limit of atomic scale physical dimension. There are many approaches to realize vertical interconnection between double stacked wafers. One of innovative methods is one-step TSV, which enables TSV process to be more cost effective comparing with the conventional TSV fabrication [1]. Fig. 1(a) shows a conventional TSV scheme to connect the two memory wafers and Fig. 1(b) is the new developed approach to connect the two memory wafers by a one-step TSV with the silicon-trench isolation. In this study, we will discuss about the issues that we encountered during this silicon-trench fabrication and how we overcome and improved them by optimizing the process and adding in some necessary inline monitor.