2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Evaluation of Residual Stress of Embedded Die Substrate with Hollow Structure for Heterogeneous Integration","authors":"M. Matsuura, T. Asano, H. Kanaya","doi":"10.1109/EPTC50525.2020.9315125","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315125","url":null,"abstract":"The residual stress in a silicon die of an embedded die substrate having a hollow structure was investigated. A silicon chip in which piezo-resistance gauges were fabricated was embedded in a hollow chamber inside of the substrate by using a newly developed process technology. The chip was mechanically held with dielectric epoxy resin at the periphery of the chip. Two kinds of the resin having a different coefficient of thermal expansion (CTE) were tested. The residual stress was measured at each critical manufacturing step. The stress was reduced after the formation of the hollow structure. The symmetric structure enabled to minimize the process-induced stress. The use of low CTE resin showed low residual stress.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"30 4 1","pages":"399-402"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89085419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient Thermal Evaluation of SiC Chip Based Power Module Under Different Cooling Conditions","authors":"G. Tang, Kazunori Yamamoto, L. Wai, Siak Boon Lim, Xiaowu Zhang","doi":"10.1109/EPTC50525.2020.9315013","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315013","url":null,"abstract":"In this paper, a SiC chip based power module with dual side cooling capability is proposed and the transient thermal characteristics of power module has been evaluated. The proposed power module eliminates the traditional direct bonded copper (DBC) substrate by replacing the DBC substrate with a dedicated copper lead frame (LF). As such the features of smaller form factor, lighter weight and lower cost have been achieved as compared with the conventional DBC substrate based power modules. To evaluate the transient thermal characteristics of the proposed SiC chip based high power module, the upcoming tasks have been conducted in this study. At first, the thermal model of the power module is constructed based on the proposed structure and recommended materials. Then the transient thermal simulation is carried out to simulate the thermal characteristics of the SiC chip based power module under different cooling conditions and power cycling profiles (on/off cycle). An appropriate cooling method and cycling profile is recommended for the power cycling test of the power module. Meanwhile, the test vehicles of the power module with the recommended materials are fabricated for the power cycling test and transient thermal evaluation. At last, the power cycling test has been carried out with a commercial power cycling test setup. The case and junction temperature of the power module at each power cycle have been measured. The simulation results match well with measurement results.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"103 1","pages":"359-364"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89125624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"bHAST, PCT, TCT reliability performance comparison of Cu-Al, PdCu-Al, Ag-Al","authors":"L. Lois, Tee Weikok, Yu Minglang, Wang Bisheng, Zhang Xi, Yee Boonhwa, Li Xiaomin, H. Younan","doi":"10.1109/EPTC50525.2020.9315083","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315083","url":null,"abstract":"Wire bond is the most common inter-connection method used to connect microchips to the terminals of a chip package. Wire bond reliability is vital to the performance of packaging device. It is vital to understand the reliability performance of different wire types under the environment of temperature, moisture and voltage bias. In this study, copper (Cu), palladium coated copper (PdCu) and silver (Ag) wires were boned to aluminum (Al) bond pad. Chlorine (Cl) and sulfur (S) contaminations were purposely introduced to epoxy molding compound (EMC) to accelerate the corrosion process. Reliability tests bHAST (biased highly accelerated stress test), pressure cooker test (PCT) and temperature cycle test (TCT) were conducted. The results showed that bHAST encountered most failures, followed by PCT. Whilst TCT encountered no failure. For the wire type, PdCu-75%Pd coverage showed the best reliability performance among all the legs. For the EMC contamination type, Cl played a significant role on wire bond reliability. Whilst, S did not impact much on wire bond reliability.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"46 1","pages":"63-67"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84705188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Non-Formaldehyde based electroless Cu deposition for Advanced Packaging","authors":"A. Pathak, Georg Friedrich, T. Teutsch","doi":"10.1109/EPTC50525.2020.9315022","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315022","url":null,"abstract":"A non-formaldehyde electroless Cu bath is evaluated in this work. Sodium hypophosphite is used as the reducing agent and electroless Cu deposition is done on Al pads using zincation as activation process. Other than copper sulfate as the copper ion source and sodium hypophosphite as the reducing agent, sodium citrate and a small amount of Ni salt are also used as the complexing agent and catalyst, respectively. The effects of pH, temperature and boric acid concentration as the buffering agent on the deposition rate and quality are evaluated. A good quality of the Cu deposits could be achieved at pH 10, temperature 70°C and boric acid concentration of 1–2 g/L at high deposition rate (200–300 nm/min). Boric acid is also found to facilitate the Cu deposition. SEM images show a uniform and a fully covered Cu layer formed on all the pads. FIB cross section images depict amorphous nature of the deposit. A solder ball bumping of Pb-free SnAgCu solder alloy was evaluated for characterization of the interfacial reaction of the deposited Cu and the solder alloy. Good adhesion and shear results observed for the bumped solder balls on the deposited Cu pads. Interfacial strength and reliability of bumped solder alloy on the pads were evaluated using multiple reflow.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"15 1","pages":"32-35"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85074774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temporary Bonding and De-bonding Process for 2.5D/3D Applications","authors":"Qin Ren, W. Loh, S. K. Neo, K. Chui","doi":"10.1109/EPTC50525.2020.9315033","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315033","url":null,"abstract":"Temporary bonding and de-bonding (TBDB) is one key technology in enabling the 2.5D/3D integration of semiconductor devices [1]. In this paper, we first evaluate two TBDB methods using different TBDB mechanism and corresponding adhesive materials, in particular for via-last Through Silicon Via (TSV) process. We compare a solvent-based TBDB method [2], [3] with another mechanical-based TBDB method. The second part of this paper analyze the process issues and root causes related to each TBDB methodology. Continuous improvement will need to rely on TBDB material and process development as well as integration optimization.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"45 1","pages":"27-31"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83748557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2D- Discrete Cosine Transform based Dynamically Controllable Image Compression Technique","authors":"Y. Kumar, Rahul Kumar, Somesh Kumar","doi":"10.1109/EPTC50525.2020.9315167","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315167","url":null,"abstract":"The Discrete Cosine Transform (DCT) is commonly used for the compression of images due to its property of high power compaction. Multiplication is a key fundamental stage in the computation of Discrete Cosine Transform (DCT) of an image. In this paper, a novel low-power, high-speed run-time configurable image compression technique based on 2D-Discrete Cosine Transform (DCT) and conventional carry lookahead adder is proposed. In the proposed implementation of 2D-DCT using configurable booth multiplier, tuning of accuracy and the size of the compressed image is realized by masking the carry propagation of configurable adder at runtime. We also calculated the various performance metrics such as Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) of conventional multiplier based 2D-DCT and proposed designs.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"203-206"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90575421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Millimeter Wave Carbon Nanotube Based Flip Chip Coplanar Interconnects","authors":"Joseph M. de Saxcé, Philippe Roux-Lévy, Chun Fei Siah, Jianxiong Wang, B. Tay, P. Coquet, D. Baillargeat","doi":"10.1109/EPTC50525.2020.9314999","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9314999","url":null,"abstract":"In this work, we investigate the performances of vertically aligned carbon nanotube (VACNT) arrays for high frequency interconnects. The frequency range of this study is the W band (75 GHz to 110 GHz). The type of interconnect is coplanar, meaning the interconnect can connect two subparts supporting a coplanar waveguide (CPW) mode. Starting from the promising results of a previously measured device [1] we suggest a way to improve the behavior of VACNT arrays interconnects. We perform full-wave modeling of a new structure that will be fabricated and tested and we compare different modelling approaches for the design of such interconnects.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"81-84"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87475788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electroless Plating with Copper Complex Ink as a Seed","authors":"Kaihwa Chew, Yousef Farraj, S. Magdassi","doi":"10.1109/EPTC50525.2020.9315010","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315010","url":null,"abstract":"Electroless or electrolytic deposition processes require the use of a very costly catalyst, usually palladium, as a seed material. Here we present the use of a copper complex as a very efficient replacement for the conventional catalysts, which can be directly printed by various technologies such as screen, gravure, and inkjet, on both 2D and 3D substrates. The copper complex can be reduced to pure copper upon short exposure to low-temperature plasma, by heating under inert atmosphere or via photonic sintering. By combining the complex with electroless plating (EP), a resistivity as low as 2.38μΩ.cm which corresponds to 72% conductivity of bulk copper can be achieved","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"36-40"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90795974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Deep Learning Analysis of 3D X-ray Images for Automated Object Detection and Attribute Measurement of Buried Package Features","authors":"R. Pahwa, T. Nwe, Richard Chang, Wang Jie, Oo Zaw Min, S. W. Ho, Ren Qin, V. S. Rao, Yanjing Yang, J. Neumann, R. Pichumani, T. Gregorich","doi":"10.1109/EPTC50525.2020.9315043","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315043","url":null,"abstract":"Failure analysis is crucial in improving semiconductor manufacturing yields. Yield improvement is done by collecting, analyzing, identifying the causes of defects, and applying corrective actions to resolve the root causes. With the ongoing miniaturization of TSVs, micro-bumps, RDLs, and other package interconnects [1], detecting defects in these buried interconnects is becoming more difficult as well as more important. Traditionally semiconductor packages are cross-sectioned to identify internal process defects such as unsolders, solder shorts, and pad misalignment. Cross-sectioning is a destructive approach, is difficult to do, and provides information in a single 2D plane only. Due to the large effort and the destructive nature of this approach, the amount of data that can be generated is typically quite limited. The development of 3D x-ray microscopy provides industry with the capability to image and analyze buried features such as micro-bumps, TSVs, and other metallic structures using a non-destructive, 3-dimensional technology [2]. At the same time, deep learning has revolutionized other technologies such as visual surveillance, predictive maintenance [3], object detection [4], and is now revolutionizing defect detection in semiconductors. When used together, the combination of 3D x-ray microscopy and deep learning is establishing a new paradigm in package inspection and metrology. In this paper, we will present a novel method for automatically detecting internal anomalies in semiconductor packages and using deep learning to assess the attributes of these interconnects. Chips representative of stacked 2.5D packages were fabricated and assembled using thermo-compression bonding. Bonding parameters were varied in order to create packages with different bond line thickness, different solder fillet shapes, and various pad alignment scenarios. A commercial 3D x-ray imaging tool was used to create high-quality tomographies of these packages. Deep-learning and computer vision-based methods were employed to automatically detect internal features and measure attributes. A three-step procedure was used for data analysis. In the first step, a bounding box was detected for each region of interest (Copper Pillar, Pad, etc.) using a modified single shot detector object model. In the second step, we isolated features within the region of interest and performed 3D segmentation on them. The third and final step utilized automated 3D metrology using the segmented regions. Robust 3D computer vision techniques were deployed to measure the extent of voids which are key attributes for the chip fabrication and process control step. This is the first part of a multi-part paper.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"190 1","pages":"221-227"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81064823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Management of the High-power Electronics in High Temperature Downhole Environment","authors":"Jiale Peng, Wei Lan, Yujun Wang, Yiming Ma, Xiaobing Luo","doi":"10.1109/EPTC50525.2020.9315026","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315026","url":null,"abstract":"The logging tool, which is utilized to detect the underground oil and gas resources, is a typical electronic instrument working in extremely high-temperature downhole environment (∼200°C) for more than 9 hours. Generally, the internal electronics can only withstand the temperature below 125°C, and thus adopting thermal management methods to ensure its normal operation turns into an urgent task. Previous researches mainly focused on the thermal management methods of the low-power electronics in the logging tool, but these methods were not suitable for high-power electronics due to a significant thermal resistance between the heat source and heat storage module. To solve this issue, a new thermal management method of integrating the heat sink and the heat storage module was proposed to enhance the heat transfer between electronics and heat storage module. The thermal performance of the structure was evaluated by the finite element method and the experiment. The simulated results show that the temperature of heat transfer and storage integrated structure is lower and more uniform than that of conventional finned heat dissipation structure, the maximum temperature of heat source drops from 165.8°C to 133.4°C, and the utilization rate of latent heat increases from 52.8% to 63.5%. Besides, inserting heat pipes to PCMs significantly reduces the maximum temperature to 110.7°C and increases the latent heat utilization rate to 99.0%. Further, the experimental results show that the electronics temperature can maintain below 125°C for 9 hours with the proposed thermal management method, which is consistent with the simulated results.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"369-375"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74775620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}