2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Tuning damage model to optimize the plastic strain distribution in electronic packaging structures","authors":"Zubin Chen, X. Long","doi":"10.1109/EPTC50525.2020.9314995","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9314995","url":null,"abstract":"Due to the cyclic loading of thermal stress, the solder joints work in the process of cyclic fatigue, and the failure behavior of solder joints in the whole process is actually a process of damage accumulation. It is feasible to study the fatigue properties of solder joints under cyclic loading. In order to achieve accurate numerical simulations, solder constitutive models have been widely concerned. The method of coupling damage variables with a constitutive model provides an effective way to achieve this goal. Under the condition of thermal cycle loading, the damage evolution corresponding to deteriorate material properties meets the basic principle framework of thermodynamics. In this framework, the damage evolution model can be derived by using continuum damage mechanics. This model is greatly simplified by averaging the micro defects of materials, as long as the established model and its derived evolution model can solve engineering problems. Based on the theoretical framework of damage constitutive model, a UMAT user material subroutine suitable for ABAQUS finite element software is completed. Through the secondary development interface of ABAQUS, the viscoplastic constitutive model parameters of coupling damage are continuously optimized, so as to achieve better simulations of the solder fatigue process. Based on the study of the coupled damage constitutive model, the UMAT is applied to the calculation of BGA packaging structure to further reflect the optimization capacity of the model for solder fatigue performance with simulation results as a good fit to the test results.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"394-398"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75352308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal and Rheological Characterization of Nonconductive Adhesive Epoxy for Process Parameter Definition of Air Cavity Mold Package Encapsulation","authors":"Marty Lorgino D. Pulutan","doi":"10.1109/EPTC50525.2020.9315084","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315084","url":null,"abstract":"A new formulated nonconductive epoxy adhesive for air cavity mold encapsulation is characterized using thermal and rheological analysis to arrive with optimized processing parameters. Based from the results, heating the epoxy under low b-stage temperature for 91 to 120 minutes showed no significant difference with mid b-stage temperature for 31 to 60 minutes in terms of physical condition, mold adhesion strength and percent cure which implies that B-staging condition can be done in an hour or less through increasing the temperature slightly higher but below the glass transition of the epoxy. Moreover, shortest possible cap-sealing cycle time was determined by gross leak test and percent cure in which heating the B-staged glue at high cap sealing temperature for 1 to 5 minutes yielded same percent cure with low cap sealing temperature for 16 to 20 minutes with no gross leaks. The C-stage curing step can be done at a temperature similar to the cap-sealing temperature but soaked for 31 to 60 minutes to achieve 100% degree of curing denoting that polymeric matrix have completely crosslinked for a reliable encapsulant.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"121-126"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75490293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient Thermal Simulation for Socket Design Evaluation & Characterization","authors":"Subramanian N.R., P. Ramamoorthy","doi":"10.1109/EPTC50525.2020.9315068","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315068","url":null,"abstract":"With the lead time to market for semiconductor products getting shorter, there is an ever increasing pressure on assembly and testing to reduce their yield time too. Sockets are the interface between the device under test (DUT) and the tester. Also, with the packaging trend towards short form factor and pitch reduction, it is a challenge to design the socket with reduced lead-time and with lesser revisions. Software simulation thus becomes inevitable not only for designing but also socket improvement. An existing socket with non-uniform temperature distribution was evaluated utilising a transient computational fluid dynamics (CFD) and thermal analysis to determine the non-uniform temperature distribution within socket as a function of air flow velocity with respect to time. Air inlet boundary conditions such as flow velocity and temperature and the opening with atmospheric pressure at the outlet were assigned to the cuboid assembly and analyses run for transient boundary conditions. Transient temperature distribution profile at various time instances were visualised to understand the temperature increase in the socket regions. CFD and thermal simulation on the evaluation of air flow helped to understand the air flow variations with the test socket assembly and the resultant rise in temperature at various pins that probe the temperature. Thus, simulation helped to optimise socket design for effective air flow and desired temperature can be achieved by understanding the flow behaviour in the test chamber.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"63 1","pages":"376-379"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79671182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Challenges in Placement Requirements for Heterogeneous Integration","authors":"C. Chong","doi":"10.1109/eptc50525.2020.9315100","DOIUrl":"https://doi.org/10.1109/eptc50525.2020.9315100","url":null,"abstract":"The growth of advance packaging especially with Heterogeneous integration and 3D stacking, starting with EMIB (Embedded Multi-die Interconnect Bridge), inFO and CoWoS (Chip-on-Wafer-on-Substrate), Foveros, SoIC (System-on-Integrated Chips) and (3D Multi-Stack) technologies, are emerging as a more cost-efficient way to achieve greater integration and IO densities. With this trend of heterogeneous integration, we can overcome Moore's law and the reliance of few key logic companies with fab capabilities below 7nm or fine pitch packaging. This paper will discuss the impact of challenges to the placement technologies and requirements on SIP in Embedded packaging.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"49 1","pages":"406-407"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80620358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Strain Response of a Semiconductor Package during Drop Test and Fast Gating Method by Bend Test","authors":"C. M. Chen, C.L. Gan, Y. Zou, M. Chung, H. Takiar","doi":"10.1109/EPTC50525.2020.9315075","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315075","url":null,"abstract":"Board level drop test was widely implemented for solder joint reliability in assembly industry, solder joint was monitored by daisy chain design and real time electrical resistant monitoring to estimate joint life since solder joint failures is the major concern in tradition. In this study, encapsulation molding compound and die crack are the observation points during drop test which is difficult to be detected real-time. Strain analysis of an electronic package during board level drop test were investigated by different levels of JEDEC drop under various drop environments. Taking drop test with 1500G/0.5ms as an example, board strain is around at center of the board area and nearby standoff of a 8 layers daisy-chain board. Meanwhile, package strain on compound side is around 600ue on a package. Main observation is package behaving as bending and the maximum axial strain is approximately 20% to 25% of board strain, both of tensile and compress. As a result, die and encapsulation have potential risks to crack induced by the bending behavior during drop shock testing.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"105 1","pages":"49-52"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80943405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Methodology to determine high precision variation in the electrical resistance of copper wires due to corrosion","authors":"Michael Joo Zhong Lim, M. Goroll, Hai Guan Loh, Zhong Chen, C. S. Tan","doi":"10.1109/EPTC50525.2020.9315088","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315088","url":null,"abstract":"In reliability testing, integrated circuit (IC) packages are subjected to accelerated stress test according to the Joint Electron Device Engineering Council (JEDEC) standards to predict the lifetime under the operating conditions. Accelerated stress test on copper wire under the influence of moisture causes corrosion which leads to increase in electrical resistance. This paper describes a methodology to measure small resistance change across the bond wires. An approach of using ceramic packages to study bond wire resistance is introduced. Customized wire bonding layout is designed using bare copper wire bonded directly on the gold-plated lead frame. Four-wire measurement setup is applied to eliminate the unwanted test lead resistance. Two types of experiments are carried out to emulate different level of corrosion, namely unbiased highly accelerated temperature and humidity stress test (uHAST) and exposure to salt-acid solution. Physical characterization such as scanning electron microscopy (SEM) inspection, transmission electron microscopy (TEM) inspection and energy dispersive x-ray spectroscopy (EDX) mapping are conducted to characterize the changes that cause the increase in electrical resistance. By using finite element method (FEM) simulation, bond wire resistance is calculated using the effective diameter of copper wires. The values from measurement and simulation are comparable with maximum deviation of 0.32%. The proposed methodology provides an accurate and reliable data collection method for corrosion effect study of copper wire bond.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"162-167"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78759889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Mechanism of u-HAST failure caused by flux residue containing bromide","authors":"Yeonseop Yu, HyoungRok Lee, J. Ha, Seungwan Kim, J. Jeon, Kang-Young Cho, Hong-Joo Baek","doi":"10.1109/EPTC50525.2020.9315186","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315186","url":null,"abstract":"Fan-Out Panel-Level Packaging (FOPLP) partly uses a printed circuit board (PCB) technology and materials for cost advantage but finer line width and spacing than PCB requires better understanding of its reliability. The present study presents the effect of residual bromide (Br−) on the reliability of FOPLP using an unbiased highly accelerated stress test (u-HAST). We prepared a package with three redistribution layers (RDLs) with under bump metallurgy (UBM) of which layers were connected through Cu micro-vias. The micro-via structure was made on Cu surface by sputtering of seed metals (Ti/Cu) followed by electroplating of Cu. We conducted u-HAST using two kinds of FOPLP products. One was processed by a flux with Br− ions during solder ball attach and the other was processed by a flux without any halide. The microstructure and chemical composition were investigated using a focused ion beam (FIB) and a transmission electron microscope (TEM) equipped with an energy dispersive spectrometer (EDS). We observed that u-HAST failure occurred only in the samples treated with the flux containing Br− ions for solder ball attach. The cross-sectional images of the failed samples show that there were delamination between the seed metals (Ti and Cu) along the via wall as well as at the bottom of the Cu micro-via. We detected bromine in the area where delamination occurred and found that the seed Ti was oxidized. We propose a failure model that delamination occurs through the combined process of forming a galvanic couple of titanium and copper in the presence of water, oxidation of titanium and diffusion of Br− ions in the titanium oxide layer.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"24 1","pages":"44-48"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81685921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and measurement for millimeter-Wave PCB and broadband RF interconnection","authors":"Kaisheng Hu","doi":"10.1109/EPTC50525.2020.9314864","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9314864","url":null,"abstract":"In this paper, one RF calibration PCB board is used to evaluate two different calibration and de-embedding methods: traditional TRL (Thru-Reflect-Line) and 2x-Thru de-embedding. The insertion loss test result from those methods are same at millimeter-wave frequency band. While TRL shows non-causality issue and higher error at phase delay. Finally, 2x-Thru is selected to evaluate several typical scenarios of high-speed interconnects: Transmission line and PCB parameter extraction (Dk, Df and Surface Roughness); RF transition between chip's BGA package to PCB; 0402 RF broadband terminator. The results from 2x-Thru meet our requirement of de-embedding quality.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"242-245"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90357580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on SMT Quality Monitoring by Auto Optical Inspection","authors":"Yungcheol Kong, J. Chae, Minkyoon Kim, Y. Lee, Kang-Young Cho","doi":"10.1109/EPTC50525.2020.9315137","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315137","url":null,"abstract":"Solder paste is the main interconnect material to use between FBGA type packages and main boards. It is consisted of different types of solder powers (in case of type 3 size is 25∼45um) and flux. Many paste parameters, such as paste composition, printing stencil aperture and reflowing profile, influence the printing performance and the reflow process of solder pastes. Flux in solder paste is classified into mainly water-soluable and no-clean flux depending on the applications. No-clean flux contained solder paste has been used in most of applications such as module, SSD etc. But, water-soluable flux contained solder paste is required in SiP module applications to prevent any possible corrosion failure due to flux residue in underfilled module. However, water-soluable flux is very sensitive by humidity in storage condition. Activation and viscosity of flux can be degraded by uncontrolled environment and caused unexpected rotation to resulted in poor solder joint self align. In general, the rheology of solder paste is complicated and affect the shape of solder joint depending on ratio of moisture absoption. If the mixture of solder paste absorb the moisture, the solder paste could be easily slumped and package component is slipped or rotated during the reflow process, result in poor solder joint quality such as non-wet. There are several methods to detect the poor solder joint quality after SMT, such as X-ray and Optical Inspection. The benefits of X-ray inspection are broad in scope due to the ability of X-rays to see through packages including. But X-ray method is restricted to used in massive production due to its poor detection resolution and low efficiency of analytical time. Especially, the poor self-align quality like non-wet joint could not be easily detected by X-ray only after SMT, so the failure samples could be outflow to customers. The main purpose of this study was to investigate effective monitoring methods for replacing sampling X-ray measurement. The existing automatic optical inspection (AOI) equipment can be used to check out the defect of the electronic products, such as solder bridging, non-wet and so on. In this paper, the solder joint self-align trend (amount of rotation) was calculated by M-AOI (Mounting-AOI of package before reflow) and S-AOI (Solidifying-AOI after reflow) data. The trends of M-AOI and S-AOI was compared with non-wet failure rate at final test and X-ray inspection result for relevant properties of solder paste such as viscosity, thixotropy, acidity and so on. AOI data shows well-matched trend with amount of rotation of package and non-wet failure rate of solder joints with regard to floor time of solder paste. As a result, new monitoring method using AOI is proposed and confirm usefulness to replace the sampling X-ray measurement as massively useful tool to check the joint quality after reflow process, and also will be used to control the moisture level of solder paste to ensure the proper rheology for SMT ","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"21 10 1","pages":"216-220"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82908502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on Contact Resistance of Connector Based on FEM","authors":"Chenzefang Feng, Xinxin Lin, Yixin Xu, F. Zhu","doi":"10.1109/EPTC50525.2020.9314867","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9314867","url":null,"abstract":"Due to the widespread use of electrical connectors while the lack of relevant in-depth theoretical models for contact states of them, this paper has investigated the electrical contact situations in contactor by establishing the theoretical model of a typical electrical connector-Subminiature version A (SMA), and used the finite element method (FEM) to analyze the actual contact state, including its contact potential distribution and the structural influence on resistance.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"51 1","pages":"403-405"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88189433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}