2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献_第9页

Practical characterization of micro fine RDL failure on PLP PLP上微细RDL失效的实际表征

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315180

K. Gunji, N. Takagi, Toshihisa Hibarino, Keiichi Tsumura

{"title":"Practical characterization of micro fine RDL failure on PLP","authors":"K. Gunji, N. Takagi, Toshihisa Hibarino, Keiichi Tsumura","doi":"10.1109/EPTC50525.2020.9315180","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315180","url":null,"abstract":"The size-unified SEMI standard for PLP was adopted last year. And several package vendors have been developing processes for the practical application of PLP substrates. [1] We apply the capacitive test technique as a RDL first interconnect inspection on PLP package. [2] Though this inspection technology, we can judge defects such as fine voids of 20um or less in the real system. A calibration is effective in further improvement of the accuracy, such as dispersion correction by warpage of the panel and packages, etc. In this paper, the effect of correction is algebraically treated by using the capacity model of RDL in order to increase the accuracy of the inspection system. And, this paper carries out the analysis on the defect detecting accuracy using the characteristic data in the actual glass carrier panel, and the practical application is discussed. In this paper, the effect of correction is algebraically treated by using the capacity model of RDL in order to increase the accuracy of the inspection system. And, this paper carries out the analysis on the defect detecting accuracy using the characteristic data in the actual glass carrier panel, and the practical application is discussed.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"19 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85217372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Lidless and lidded Flip Chip Packages for Advanced Applications 用于高级应用的无盖和有盖倒装芯片封装

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315021

G. Refai-Ahmed, Huayan Wang, S. Ramalingam, N. Karunakaran, K. Pan, S.B. Park, Alegesen Soundarajan, Sreedharan Kelappen Kanaran, C. Chung, Yu Lung Huang

{"title":"Lidless and lidded Flip Chip Packages for Advanced Applications","authors":"G. Refai-Ahmed, Huayan Wang, S. Ramalingam, N. Karunakaran, K. Pan, S.B. Park, Alegesen Soundarajan, Sreedharan Kelappen Kanaran, C. Chung, Yu Lung Huang","doi":"10.1109/EPTC50525.2020.9315021","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315021","url":null,"abstract":"Thermal management and reliability are two critical aspects of designing an advanced flip chip package. Lidded and lidless are one of the most important variations depending on specific applications in a view of manufacturing cost, compactness, reliability, and thermal performance. In recent years, lidless packages are widely adopted in high power electronics because its superiorities of better thermal performance, compactness, and cost-effectiveness. In the meantime, various novel designs of lidless package haven been proposed to resolve the potential thermomechanical reliability challenges. This paper reviews the overall thermal resistance and thermal-induced reliability issues of lidless and lidded flip chip packages with different design parameters, such as the properties and thickness of the thermal interface material (TIM), heatsink loading pressure, and the presence of the heat spreader/lid and heatsink. Factors that determine thermal resistance of the TIMs are summarized. They include thickness of the TIM, volume fraction and distribution of the filler particles. Some novel designs and technologies for better thermomechanical reliability of lidless package are reviewed. New designs of the lid and heatsink as well as advanced thermal solutions are also reviewed. Challenges and solutions of lidless package during thermal cycling and power cycling are reviewed.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"52 1","pages":"104-111"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85291284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A Study to Reduce Molding Film Defects During Vacuum Lamination Process 减少真空层压成型膜缺陷的研究

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315116

Lau Boon Long, D. Ho, S. Ps, C. T. Chong

{"title":"A Study to Reduce Molding Film Defects During Vacuum Lamination Process","authors":"Lau Boon Long, D. Ho, S. Ps, C. T. Chong","doi":"10.1109/EPTC50525.2020.9315116","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315116","url":null,"abstract":"In this paper, an evaluation study was performed to reduce the epoxy molding film defects during vacuum lamination process. This epoxy mold film was vacuum laminated on fanout reconfigured silicon substrate; which was recognized as one of the key process step in fan-out wafer level packaging FO-WLP technology process flows. The key challenges to overcome by applying this process is to reduce the critical voids defects, seam line defects and film induced warpage which could lead to high yield loss if RDL layers build on top of this surface. This paper evaluated the effect of mold film preparation conditions and laminated substrate pre-treatment conditions on reducing the voids formations after lamination process. The maximum thickness of stacked mold film in correlating with film material properties was evaluated to meet the low warpage conditions for semiconductor process tool handling requirements. The optimized vacuum laminator process parameters such as vacuum process time, pressurization temperature and pressure was evaluated to achieve the significant reduction of voids, seam line and mold crack defects. These impacts and defects reduction trends in correlation with process parameters are useful to act as guidelines for defect issues troubleshooting, new material process parameters optimization and continuous process window improvement.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"130-134"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79496505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Automatic Chip-Package Co-Design Flow for Multi-core Neuromorphic Computing SiPs 多核神经形态计算sip的芯片封装自动协同设计流程

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315089

Jingjing Lan, V. P. Nambiar, Rheeshaalaen Sabapathy, R. Dutta, C. T. Chong, M. D. Rotaru, Kuang-Kuo Lin, S. Bhattacharya, K. Chai, A. Do

{"title":"An Automatic Chip-Package Co-Design Flow for Multi-core Neuromorphic Computing SiPs","authors":"Jingjing Lan, V. P. Nambiar, Rheeshaalaen Sabapathy, R. Dutta, C. T. Chong, M. D. Rotaru, Kuang-Kuo Lin, S. Bhattacharya, K. Chai, A. Do","doi":"10.1109/EPTC50525.2020.9315089","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315089","url":null,"abstract":"The complexity and cost of system-on-chip (SoC) designs keep increasing every year, which has progressively led to more opportunities for 2.5D System-in-Package (SiP) design. While 2.5D integration technology offers advantages for heterogeneous chiplet-based systems, it also poses challenges of a more complex overall design flow with limited EDA tools support, physical design optimization issues, interposer floor-planning difficulties and complex system-level verification. Furthermore, accurate inter-chiplet connection modeling, chiplet characterization and top-level simulation activities are also needed for comprehensive verification of SiPs. To tackle these challenges, we share an automated chiplet-based codesign flow: built on the backbone with standard EDA design tools, an automatic SiP register transfer language (RTL) generator is developed for top-level SiP netlist generation; inter-chiplet connection routing with chip assembly router and parasitic extraction tools; interposer design and bumps placement with the foundry defined redistribution layer (RDL).","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"44 1","pages":"77-80"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86702378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Process and Consumable Development for Silver Wire Bonding 银线键合工艺及耗材开发

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315061

Tao Xu, Joseph Madril, Omid Niayesh, P. Klaerner

{"title":"Process and Consumable Development for Silver Wire Bonding","authors":"Tao Xu, Joseph Madril, Omid Niayesh, P. Klaerner","doi":"10.1109/EPTC50525.2020.9315061","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315061","url":null,"abstract":"With increased demands, power modules are often required to run at higher temperatures with improved reliability. Solder joint fatigue is a major failure mode for current power modules. Silver sintering die-attach technology significantly improves power module reliability. Due to the reliability problem at the interface between aluminum (Al) wire and a silver (Ag) layer, bonding Ag wire to the Ag layer is highly desired. Ag wire is harder and stiffer than Al wire, resulting in much higher wear and significantly reduced lifetime of consumables. This paper introduced the K&S CuEx™ bond tool and studied coupling and interaction between the bond tool and Ag wire. By optimizing the bonding process, the CuEx™ bond tools achieved 400,000 touchdowns, which is 80× more than the standard bond tool lifetime of 5,000 touchdowns. The difference between the front-cut and rear-cut process is discussed. By studying and optimizing the cutting process, the standard rear-cut cutter blade lifetime is increased 4×, from 50,000 cuts to 200,000 cuts. It is observed that Ag wire did not wear a wire guide much faster than Al wire. The standard wire guide exhibited minimum wear after 200,000 bonds.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"176-181"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88673039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials 不同临时键合材料对通硅中间层(TSI)晶圆翘曲的影响

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315102

W. Loh, K. Chui

引用次数: 2

Reliability Study of Copper Pillar Bump Interconnects for Acoustic Wave - Wafer Level Package 声波-晶圆级封装铜柱凸点互连可靠性研究

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315058

J. Schober, K. Nicolaus, G. Feiertag

引用次数: 1

Surface Characterization and Leadframe-to-Mold Adhesion Performance of Oxidation-Roughened Leadframes 氧化粗化引线框的表面表征和引线框与模具的粘附性能

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315090

Matthew M. Fernandez, Richard Jan C. Malifer

{"title":"Surface Characterization and Leadframe-to-Mold Adhesion Performance of Oxidation-Roughened Leadframes","authors":"Matthew M. Fernandez, Richard Jan C. Malifer","doi":"10.1109/EPTC50525.2020.9315090","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315090","url":null,"abstract":"Leadframe surface roughening increases the leadframe-to-mold interfacial adhesion strength through mechanical locking and free-radical bonding mechanism. On this study, two different oxidation-roughened leadframes were successfully evaluated through leadframe surface characterization and leadframe-to-mold adhesion performance. Leadframe surface morphology characterization showed that both Leadframes have the same needle-like microstructure at zero-hour. After high temperature anneal, Leadframe A evolved into coarser structure while Leadframe B remains stable. Hypothesis tests confirmed that Leadframe B have higher surface stability than the Leadframe A upon exposure to high temperature annealing process. Leadframe-to-mold adhesion performance through Button Shear Test revealed that mold adhesion strength of Leadframe B is consistently higher than Leadframe A at Ag and Cu regions. Hypothesis tests also confirmed that Leadframe B have stable shear strength upon exposure to high temperature annealing process while Leadframe A showed a significant degradation of shear strength after annealing process. The leadframe-to-mold adhesion performance through SAM showed that the Leadframe B has better Leadframe-to-mold adhesion than the leadframe A. The mold adhesion improvements can be attributed to the microstructural and roughness stability of the surface. Leadframe B showed stable microstructure upon exposure to high temperature annealing process resulted to high and stable mold shear strength and leadframe-to-mold adhesion.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"116-120"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90970521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fan-Out Packaging with Thin-film Inductors 薄膜电感的扇出封装

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315018

Soh Siew Boon, H. Wee, Simon Lim Siak Boon, Sharon Lim Pei Siang, R. Singh, S. Raju

{"title":"Fan-Out Packaging with Thin-film Inductors","authors":"Soh Siew Boon, H. Wee, Simon Lim Siak Boon, Sharon Lim Pei Siang, R. Singh, S. Raju","doi":"10.1109/EPTC50525.2020.9315018","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315018","url":null,"abstract":"Fan-out Wafer Level Packaging is widely and commonly adopted to ease implementation for low-cost packaging. It offers an enhanced solution of standard wafer-level packaging (WLP), which gained popularity for its application in embedding integrated circuitry into smaller packaging approaches. This development involves the study of voltage regulators using an integrated thin-film inductor technology with a laminated magnetic core. Voltage regulators are essential devices in microprocessors, systems-on-chip, and other electronic components to maintain the consistency in the desired operating voltage for the circuits. The inductors and regulators can be co-optimized for achieving good electrical performance. For demonstrating the FOWLP integration of the voltage regulator, the thin-film inductors are embedded into a Fan-out package along with the CMOS controller ASIC. The packaging solution targets to provide high-efficiency power conversion. The electrical characterization results indicated that the low-loss inductor with a peak quality factor of 21 is useful in high-efficiency power conversion.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"77 1","pages":"449-452"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72814093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Combining low-dk properties with fast processing and low temperature curing for an advanced packaging dielectric material for 5G 低dk特性与快速加工、低温固化相结合的5G先进封装介质材料

2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315181

P. Miskiewicz, G. Larbig, G. Noya, J. Pradella, F. Meyer, M. Koch

引用次数: 0