Practical characterization of micro fine RDL failure on PLP

Abstract

The size-unified SEMI standard for PLP was adopted last year. And several package vendors have been developing processes for the practical application of PLP substrates. [1] We apply the capacitive test technique as a RDL first interconnect inspection on PLP package. [2] Though this inspection technology, we can judge defects such as fine voids of 20um or less in the real system. A calibration is effective in further improvement of the accuracy, such as dispersion correction by warpage of the panel and packages, etc. In this paper, the effect of correction is algebraically treated by using the capacity model of RDL in order to increase the accuracy of the inspection system. And, this paper carries out the analysis on the defect detecting accuracy using the characteristic data in the actual glass carrier panel, and the practical application is discussed. In this paper, the effect of correction is algebraically treated by using the capacity model of RDL in order to increase the accuracy of the inspection system. And, this paper carries out the analysis on the defect detecting accuracy using the characteristic data in the actual glass carrier panel, and the practical application is discussed.