Matthew M. Fernandez, Marty Lorgino D. Pulutan, A. Arano
{"title":"The Effect of Strip Argon Plasma Cleaning onto the PPF and Ag-plated Cu Leadframe Surfaces","authors":"Matthew M. Fernandez, Marty Lorgino D. Pulutan, A. Arano","doi":"10.1109/EPTC50525.2020.9315017","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315017","url":null,"abstract":"The effect of plasma power and plasma time parameters on the PPF and Ag-plated surfaces were successfully evaluated through surface characterization and leakage functional test. Surface characterization showed that the hydrophobic surface of PPF-plated and Ag-plated leadframes transformed into hydrophilic surface after application of different levels of plasma power and time which is an indication of improvement on wettability. Surface roughness showed that long exposure time can trigger further roughening of the PPF surface. Statistical analysis suggest that the plasma parameters should be kept at leg 6 (mid power, low time). Furthermore, leakage performance of the device showed that increasing the plasma time parameter affect the current leakage performance. Extreme conditions of plasma setting can result to re-deposition of unwanted elements on top of die due to over-etching. The recommended plasma parameter setting showed well-centered current distribution and zero occurrence of leakage failure.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"98 1","pages":"127-129"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80684218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermoelectrics in cryogenic cooling","authors":"Avijit Goswami, S. Kanetkar","doi":"10.1109/EPTC50525.2020.9315047","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315047","url":null,"abstract":"A use case for thermoelectric coolers (TEC) in cryogenic cooling application is presented where the heat load is small and the required temperature difference between the hot and cold sides ($Delta mathrm{T}$) is very high. The application shown here is the cooling of image sensors used in telescopes. These sensors need to be cooled to below −90C (to improve signal to noise ratio) with a heat load of less than 1W at an ambient temperature of $20mathrm{C}$. This has been traditionally done using liquid nitrogen, however, this method requires high maintenance in having to periodically refill nitrogen. A TEC-based solution can offer a significant benefit in terms of lower cost and maintenance. A multi-stage TEC is generally well suited for applications which require a large $Delta mathrm{T}$ and low heat load. In order to determine if a commercially available multistage TEC is enough to meet the $Delta mathrm{T}$ requirement, an experimental setup was created using a vacuum chamber containing TECs inside and a liquid cooling plate on the bottom to remove the heat load from the hot side. Different types of TEC stacks were tested under an applied heat load of 0.6W on the cold side. It was found that although there are many commercially available multi-stage TECs for cryogenic applications, it alone is not enough to achieve the required $Delta mathrm{T}$ of 110C. Also, adding more than 4 or 5 stages to the multistage TEC is not very effective due to the very low COP and the exponential rise of heat dissipation in the lower stages. The maximum $Delta mathrm{T}$ that can be achieved by one multi-stage TEC was found to be only around 90C at a heat load of 0.6W. It is shown here that in order to overcome the $Delta mathrm{T}$ shortfall, an additional layer of 3 single-stage TECs (in parallel) needs to be added at the bottom of the multi-stage TEC in order to increase the total $Delta mathrm{T}$ closer to the required value (110C).","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"355-358"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88271596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Redistribution Layer Defect Classification Using Computer Vision Techniques And Machine Learning","authors":"Sachin Dangayach, Prayudi Lianto, S. Mishra","doi":"10.1109/EPTC50525.2020.9315117","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315117","url":null,"abstract":"In the semiconductor industry, defects are yield killers and the detection/classification of which can be expensive as well as time consuming. To overcome this challenge, we propose a solution involving Computer Vision Techniques and Machine Learning to accomplish defect binning procedure in typical wafer-level packaging scenario, focusing on 2um L/S redistribution layer (RDL) features. With this approach, inspection cycle time is reduced, thereby driving faster product development.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"237-241"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85844351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Micromorphology analysis of Sn-3.0Ag-0.5Cu solder under compression in wide ranges of temperature and strain rate","authors":"Junmeng Xu, Chuantong Chen, X. Long","doi":"10.1109/EPTC50525.2020.9315063","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315063","url":null,"abstract":"The microstructure and mechanical properties of Sn-3.0Ag-0.5Cu (SAC305) under different working conditions were studied by static compression tests. The constitutive behaviour of SAC305 material with wide ranges of temperature and strain rate was obtained and correlated with the micromorphology on the specimen surface in this paper. With the temperature varies, the micromorphology of the solder specimens changed significantly. Specifically, as the temperature increases, more compression fringes along the loading direction appeared on the surface of the specimen, and the length of the fringes was elongated. Moreover, the mechanical properties of the solder showed obvious softening phenomenon, that is, the compressive strength decreased gradually. With the increase of the loading strain rate, the micromorphology showed the opposite evolution law compared with the consequences when the temperature increases. That is, the compression fringes gradually decrease and shorten, and the strength increased continuously, which shows an obvious hardening phenomenon. Under the condition of high temperature and low strain rate, a macro crack with the degree of 45° with respect to the compression axis can also be found on the surface of static compression specimen, and its length and width changed regularly with temperature and strain rate.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"66 1","pages":"312-315"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73970373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Introduction of Reverse Pyramid Configuration with Package Construction Characterization for Die Tilt Resolution of Highly Sensitive Multi-Stacked Dice Sensor Device","authors":"Antonio R. Sumagpang, F. R. Gomez, R. Rodriguez","doi":"10.1109/EPTC50525.2020.9315184","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315184","url":null,"abstract":"The paper focuses in addressing the die tilting issue of new device during new product introduction which consists of multi-stacked dice (two accelerometers plus one temperature sensor) during die attach process. All (100%) of qualification lots were affected with an average of 8000 defect parts per million (ppm) per lot. Die placement optimization, package construction characterization and simulation through Finite Element (FE) analysis were done, resulting to the reverse pyramid configuration of the device as the ultimate solution. This configuration validated and resolved the required die placement stability that resulted to elimination of die tilting issues from 8000 ppm to 0 ppm. For future works, the configuration could be applied for packages with similar construction.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"13 1","pages":"140-146"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74799657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Zou, M. Chung, Tracy Tennant, C.L. Gan, Yun-Ting Hsu, H. Takiar
{"title":"Investigation of Shear Strength and Temperature Cycling Performance of Bi-doped Sn-Ag-Cu Solder Joints","authors":"Y. Zou, M. Chung, Tracy Tennant, C.L. Gan, Yun-Ting Hsu, H. Takiar","doi":"10.1109/EPTC50525.2020.9315072","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315072","url":null,"abstract":"The shear strength, shear fracture mode, and interfacial reaction of Bi-doped SnAgCu solder ball under thermal aging at 150°C and 175°C for up to 250h were investigated in this study. Five different combinations of solder balls and substrate finishes were fabricated and tested including: SAC405Ni005-Bi and SAC105Ni005 on organic solderability preservative (OSP); SAC405Ni005-Bi, SAC305, and SAC302 on electrolytic NiAu (eNiAu). The interfacial intermetallic compound (IMC) of SAC105Ni005 on Cu-OSP, SAC305 on eNiAu, SAC405Ni005-Bi on Cu-OSP, SAC305 on eNiAu, SAC405Ni005-Bi on Cu-OSP and eNiAu are identified as (Cu, Ni)6Sn5, which confirms that Bi atom is not involved in the interfacial reaction. Whereas the IMC of SAC302 on eNiAu is identified as (Ni, Cu)3Sn4, which significantly differs from the other combinations. In addition, the formation of second phase IMC Cu3Sn and (Ni, Cu)3Sn4 were further observed on SAC405Ni005-Bi with Cu-OSP and eNiAu after thermal aging for 250h, respectively. The result of ball shear test at 600 um/sec shear speed showed that as-assembled SAC405Ni005-Bi gives approximately 70% bulk strength increase as compared to SAC305 and SAC302, which confirms the strengthening effect of Bi addition. Furthermore, the shear test after thermal aging indicated that the interfacial shear strength of SAC405Ni005-Bi on Cu-OSP is approximately 40% greater than SAC405Ni005-Bi on eNiAu, which confirms that IMC combination of (Cu, Ni)6Sn5 and Cu3Sn is more robust than that of (Cu, Ni)6Sn5 and (Ni, Cu)3Sn4 to resist interfacial shear stressing. As a result, temperature cycling is performed to validate the performance of Bi-doped solder alloy.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"286-290"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75014906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yam Lip Huei, L. Ting, Chong Kim Hui, B. S. Kumar, Chan Li-san, Fritzsche, Sebastián
{"title":"Solder Paste Transfer Via Pattern Tape Technology","authors":"Yam Lip Huei, L. Ting, Chong Kim Hui, B. S. Kumar, Chan Li-san, Fritzsche, Sebastián","doi":"10.1109/EPTC50525.2020.9315055","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315055","url":null,"abstract":"Stencil Printing Technology is currently a high throughput process for solder or adhesive materials deposition used in SMT and bumping process. With growth of heterogenous integration in the advanced semiconductor packaging is driving more stringent fine pitch application requirements. Disadvantages of Stencil Printing Technology for ultrafine pitch application, i.e. MicroLED Chip Attach, is restricted by stencil design (opening size) which resulted in frequent clogging of stencil and thus increase cost. Hence a “stencil-less” technology for solder paste deposition via novel tape or film transfer process will be studied in this work. The paste transfer under development will require the use of low temperature profile to enable paste to deposit onto the substrate (receiver) and maintain structural integrity, probably in a semi state of paste form which can be subjected for Si die or microchip attach for reflow soldering to complete good solder interconnection during mass assemblies process.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"30 1","pages":"297-301"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81924828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of Package Inductance on Stability of mm-Wave Power Amplifiers","authors":"Y. Jeon, R. Kumarasamy","doi":"10.1109/EPTC50525.2020.9315069","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315069","url":null,"abstract":"It is known that mm-Wave power amplifiers can suffer from deterioration of power gain and efficiency due to package parasitic. This paper addresses specifically the impact of package inductances on the stability. Two methods are suggested to improve the stability, which are adoption of wide-band RC networks and splitting power supplies and grounds for multi-stage amplifiers.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"84 1","pages":"255-256"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83875847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Che, Yeow Chon Ong, H. Ng, C.L. Gan, Christopher D. Glancey, H. Takiar
{"title":"Study on Package Strength of uMCP (Multichip Package) for Mobile Application through Three-Point Bending Test and Simulation","authors":"F. Che, Yeow Chon Ong, H. Ng, C.L. Gan, Christopher D. Glancey, H. Takiar","doi":"10.1109/EPTC50525.2020.9315126","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315126","url":null,"abstract":"Package strength becomes challenging and issue for thin package used in mobile application. Package with low strength may result in package failure such as inside die cracking or package cracking through epoxy mold compound (EMC) when package is subjected to external loading from assembly process or field application. Package design and strength assessment methodology are essential for robust package used in mobile application. In this study, uMCP package is selected to demonstrate package strength investigation and improvement. Three-point bend (3PB) testing approach and finite element analysis (FEA) method are adopted for package strength study. A strain-controlled methodology is developed for package strength assessment. FEA simulation results show that mold cap thickness and mold clearance are 2 key factors for package strength. Die strength is another key factor for robust package strength design. In addition, effect of EMC material on package strength is also investigated.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"68 1","pages":"57-62"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90756252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhiwen Li, Shu Ming Yip, Yee Wai Fung, Haibin Chen
{"title":"A Packaging Solution to Enable Moisture Sensitivity Level 1 Zero Delamination for Leaded Surface Mount Device Package","authors":"Zhiwen Li, Shu Ming Yip, Yee Wai Fung, Haibin Chen","doi":"10.1109/EPTC50525.2020.9315066","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315066","url":null,"abstract":"Surface mount technology (SMT) is widely used and being the major component assembly technology, it offers more reliable assembly with less package weight, less printing circuit board (PCB) area and much faster assembly speed, when compared to conventional through-hole (TH) technology. The surface mount device (SMD) packages structure, materials, processes, and assembly process are quite different from through-hole packages, as well as quality requirements. The SMD package are mounted on board by soldering process, it can be sensitive to moisture when exposing to environment, the moisture content of the SMD packages must be well controlled in order to prevent the delamination occurring during board solder reflow process. To understanding the moisture sensitivity performance of SMD packages, moisture sensitivity level (MSL) classification is introduced to identify the SMD packages performance from MSL 1 to MSL 6 at a reflow temperature of 260°C. Package achieved the most robust level MSL 1 can be interpreted as not sensitive to moisture, the floor life is unlimited under typical room temperature and humidity, also do not need dry packing as special control. As the continuous tightening of automotive requirements, package delamination level after MSL 1 become more and more concerned as a semiconductor packaging focusing point, zero delamination after MSL 1 is being pushed to be a solid requirement by semiconductor customers. The delamination between epoxy molding compound (EMC) and leadframe (LF), as well as die attach adhesive (DA) and LF are well known and understood, and with quite mature solutions e.g. enhancing the interfacial adhesion etc. In this study, a unique MSL 1 delamination symptom in the area around DA fillet is reviewed and discussed, root cause is identified by surface analysis techniques, and links to the die attach effect. The potential optimization in terms of packaging materials and process is proposed and validated by assembled packages, which subject to MSL 1 conditions and 3 times reflow at 260°C. Material characterization on the optimized packaging material is conducted to understand and verify the material impact, delamination levels are checked by C-Mode Scanning Acoustic Microscope (C-SAM) to assess the package interfaces after MSL 1 and reflow. Result shows zero delamination after MSL 1 can be achieved by the proposed optimization, a packaging solution can be concluded to enable MSL 1 zero delamination for leaded SMD package.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"187 1","pages":"135-139"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85629147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}