2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献

{"title":"Redistribution Layer Defect Classification Using Computer Vision Techniques And Machine Learning","authors":"Sachin Dangayach, Prayudi Lianto, S. Mishra","doi":"10.1109/EPTC50525.2020.9315117","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315117","url":null,"abstract":"In the semiconductor industry, defects are yield killers and the detection/classification of which can be expensive as well as time consuming. To overcome this challenge, we propose a solution involving Computer Vision Techniques and Machine Learning to accomplish defect binning procedure in typical wafer-level packaging scenario, focusing on 2um L/S redistribution layer (RDL) features. With this approach, inspection cycle time is reduced, thereby driving faster product development.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"237-241"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85844351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dual-band one-sided directional slot array antenna for 10GHz and 24GHz application","authors":"Y. Yamashita, H. Kanaya","doi":"10.1109/EPTC50525.2020.9315070","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315070","url":null,"abstract":"This paper presents a design of one-sided directional dual band slot array antenna for both 10GHz and 24GHz application. The antenna element is composed of a top metal, a dielectric substrate, and a bottom metal layer. This antenna is divided into a part corresponding to the upper X-band 2 array and to the lower K-band 4 array antenna. The antenna element is connected to the coplanar waveguide (CPW) feed line. From the simulation and measurement result of the return loss and antenna gain are presented in this paper. The peak gain of proposed antenna is 6.32 dBi at 9.6 GHz and 10.40 dBi at 24 GHz.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"5 1","pages":"251-254"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85780869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal Characterization of 2.5D FCBGA for GPU Application","authors":"Tang-Yuan Chen, Bing-Yuan Huang","doi":"10.1109/EPTC50525.2020.9315035","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315035","url":null,"abstract":"2.5D Integrated Circuit package is very important for high- performance applications. The shrinkage in package size, cost reduction and improving thermal performance are driving the development of 2.5D Integrated Circuit. The development of 2.5D technology faces the challenge of thermal path and new structure. The present study applied three-dimensional finite volume methods to simulate the thermal behavior and the allocation of hot spots in the 2.5D package. The results of molding analysis revealed that the thermal resistance between molding/non-molding and expose-die packaging would influence the manufacturability and reliability of the package. In order to reduce the thermal resistance of package and the die to die integration, a design monitoring the installation ratio between package and substrate were investigated. The results of simulation indicate that the power map is non-uniform. The hot spot occurs as the ratio of die/power is over 25 %. The designs of implementing a shielding of ASIC/HBM and interconnect structure of package/substrate improve the maximum power of 2.5D FCBGA about 35~40%. The results of numerical analysis indicate that the above mentioned advance 2.5D IC structure design would lead to better thermal dissipation. The enhancements in the thermal dissipation behaviors are ascribed to the thermal path and the appropriate hot spot location layout. The 2.5D Integrated Circuit package mechanism and the design guidance for engineering application will be presented and discussed in this paper.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"479-482"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74884142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Micromorphology analysis of Sn-3.0Ag-0.5Cu solder under compression in wide ranges of temperature and strain rate","authors":"Junmeng Xu, Chuantong Chen, X. Long","doi":"10.1109/EPTC50525.2020.9315063","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315063","url":null,"abstract":"The microstructure and mechanical properties of Sn-3.0Ag-0.5Cu (SAC305) under different working conditions were studied by static compression tests. The constitutive behaviour of SAC305 material with wide ranges of temperature and strain rate was obtained and correlated with the micromorphology on the specimen surface in this paper. With the temperature varies, the micromorphology of the solder specimens changed significantly. Specifically, as the temperature increases, more compression fringes along the loading direction appeared on the surface of the specimen, and the length of the fringes was elongated. Moreover, the mechanical properties of the solder showed obvious softening phenomenon, that is, the compressive strength decreased gradually. With the increase of the loading strain rate, the micromorphology showed the opposite evolution law compared with the consequences when the temperature increases. That is, the compression fringes gradually decrease and shorten, and the strength increased continuously, which shows an obvious hardening phenomenon. Under the condition of high temperature and low strain rate, a macro crack with the degree of 45° with respect to the compression axis can also be found on the surface of static compression specimen, and its length and width changed regularly with temperature and strain rate.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"66 1","pages":"312-315"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73970373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer Warpage Evaluation of Through Si Interposer (TSI) with Different Temporary Bonding Materials","authors":"W. Loh, K. Chui","doi":"10.1109/EPTC50525.2020.9315102","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315102","url":null,"abstract":"This paper investigate the evolution of wafer warpage at different stages of a Through Si interposer (TSI) process flow, with reference to 2 different types of temporary bonding material. Comparison was done between solvent based and mechanical based debonding adhesives. The TSI fabrication includes 4 layers Cu damascene (BEOL) metal, front-side UBM, post-bonding backgrinding, TSV reveal etch and backside UBM.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"70 1","pages":"268-272"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78958199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Practical characterization of micro fine RDL failure on PLP","authors":"K. Gunji, N. Takagi, Toshihisa Hibarino, Keiichi Tsumura","doi":"10.1109/EPTC50525.2020.9315180","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315180","url":null,"abstract":"The size-unified SEMI standard for PLP was adopted last year. And several package vendors have been developing processes for the practical application of PLP substrates. [1] We apply the capacitive test technique as a RDL first interconnect inspection on PLP package. [2] Though this inspection technology, we can judge defects such as fine voids of 20um or less in the real system. A calibration is effective in further improvement of the accuracy, such as dispersion correction by warpage of the panel and packages, etc. In this paper, the effect of correction is algebraically treated by using the capacity model of RDL in order to increase the accuracy of the inspection system. And, this paper carries out the analysis on the defect detecting accuracy using the characteristic data in the actual glass carrier panel, and the practical application is discussed. In this paper, the effect of correction is algebraically treated by using the capacity model of RDL in order to increase the accuracy of the inspection system. And, this paper carries out the analysis on the defect detecting accuracy using the characteristic data in the actual glass carrier panel, and the practical application is discussed.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"19 1","pages":"233-236"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85217372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Packaging Solution to Enable Moisture Sensitivity Level 1 Zero Delamination for Leaded Surface Mount Device Package","authors":"Zhiwen Li, Shu Ming Yip, Yee Wai Fung, Haibin Chen","doi":"10.1109/EPTC50525.2020.9315066","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315066","url":null,"abstract":"Surface mount technology (SMT) is widely used and being the major component assembly technology, it offers more reliable assembly with less package weight, less printing circuit board (PCB) area and much faster assembly speed, when compared to conventional through-hole (TH) technology. The surface mount device (SMD) packages structure, materials, processes, and assembly process are quite different from through-hole packages, as well as quality requirements. The SMD package are mounted on board by soldering process, it can be sensitive to moisture when exposing to environment, the moisture content of the SMD packages must be well controlled in order to prevent the delamination occurring during board solder reflow process. To understanding the moisture sensitivity performance of SMD packages, moisture sensitivity level (MSL) classification is introduced to identify the SMD packages performance from MSL 1 to MSL 6 at a reflow temperature of 260°C. Package achieved the most robust level MSL 1 can be interpreted as not sensitive to moisture, the floor life is unlimited under typical room temperature and humidity, also do not need dry packing as special control. As the continuous tightening of automotive requirements, package delamination level after MSL 1 become more and more concerned as a semiconductor packaging focusing point, zero delamination after MSL 1 is being pushed to be a solid requirement by semiconductor customers. The delamination between epoxy molding compound (EMC) and leadframe (LF), as well as die attach adhesive (DA) and LF are well known and understood, and with quite mature solutions e.g. enhancing the interfacial adhesion etc. In this study, a unique MSL 1 delamination symptom in the area around DA fillet is reviewed and discussed, root cause is identified by surface analysis techniques, and links to the die attach effect. The potential optimization in terms of packaging materials and process is proposed and validated by assembled packages, which subject to MSL 1 conditions and 3 times reflow at 260°C. Material characterization on the optimized packaging material is conducted to understand and verify the material impact, delamination levels are checked by C-Mode Scanning Acoustic Microscope (C-SAM) to assess the package interfaces after MSL 1 and reflow. Result shows zero delamination after MSL 1 can be achieved by the proposed optimization, a packaging solution can be concluded to enable MSL 1 zero delamination for leaded SMD package.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"187 1","pages":"135-139"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85629147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Package Inductance on Stability of mm-Wave Power Amplifiers","authors":"Y. Jeon, R. Kumarasamy","doi":"10.1109/EPTC50525.2020.9315069","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315069","url":null,"abstract":"It is known that mm-Wave power amplifiers can suffer from deterioration of power gain and efficiency due to package parasitic. This paper addresses specifically the impact of package inductances on the stability. Two methods are suggested to improve the stability, which are adoption of wide-band RC networks and splitting power supplies and grounds for multi-stage amplifiers.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"84 1","pages":"255-256"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83875847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Study of Copper Pillar Bump Interconnects for Acoustic Wave - Wafer Level Package","authors":"J. Schober, K. Nicolaus, G. Feiertag","doi":"10.1109/EPTC50525.2020.9315058","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315058","url":null,"abstract":"Replacing solder ball interconnects through copper pillar bump (CPB) interconnects on acoustic wave components (AWC) like SAW (surface acoustic wave) filters saves valuable chip space and facilitates chip miniaturization. In this contribution, we present our very first assembly and reliability results for CPBs on lithium niobate chips with TFAP(tm) (Thin Film Acoustic Package) for SAW filters. The CPBs consist of a Cu/Ni/SnAg layer stack and are soldered on a test board with Cu/Ni/Au finish. Leaving aside premature failures due to poor soldering, CPBs withstand 770 cycles of RCoT (Rapid Change of Temperatur, −40°C / + 125°C) reliability testing. The solder joints were investigated via cross section micrographs. Additionally, uHAST (Accelerated Moisture Resistance - unbiased HAST), DH (Dry Heat) and DHSS (Damp Heat Steady State) reliability tests were performed.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"85-89"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91283273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process and Consumable Development for Silver Wire Bonding","authors":"Tao Xu, Joseph Madril, Omid Niayesh, P. Klaerner","doi":"10.1109/EPTC50525.2020.9315061","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315061","url":null,"abstract":"With increased demands, power modules are often required to run at higher temperatures with improved reliability. Solder joint fatigue is a major failure mode for current power modules. Silver sintering die-attach technology significantly improves power module reliability. Due to the reliability problem at the interface between aluminum (Al) wire and a silver (Ag) layer, bonding Ag wire to the Ag layer is highly desired. Ag wire is harder and stiffer than Al wire, resulting in much higher wear and significantly reduced lifetime of consumables. This paper introduced the K&S CuEx™ bond tool and studied coupling and interaction between the bond tool and Ag wire. By optimizing the bonding process, the CuEx™ bond tools achieved 400,000 touchdowns, which is 80× more than the standard bond tool lifetime of 5,000 touchdowns. The difference between the front-cut and rear-cut process is discussed. By studying and optimizing the cutting process, the standard rear-cut cutter blade lifetime is increased 4×, from 50,000 cuts to 200,000 cuts. It is observed that Ag wire did not wear a wire guide much faster than Al wire. The standard wire guide exhibited minimum wear after 200,000 bonds.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"176-181"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88673039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}