2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献

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Dry Etched Through SiC Via (TSiCV) Process Analysis Using DOE Modeling 基于DOE模型的干蚀刻SiC通孔工艺分析
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315121
P. Mackowiak, M. Schiffer, Martin Scheider-Ramelow, K. Lang
{"title":"Dry Etched Through SiC Via (TSiCV) Process Analysis Using DOE Modeling","authors":"P. Mackowiak, M. Schiffer, Martin Scheider-Ramelow, K. Lang","doi":"10.1109/EPTC50525.2020.9315121","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315121","url":null,"abstract":"This paper describes the research on modelling the etching parameters of SiC using RIE. The experiments were performed using a design of experiments (DOE) with a total 78 experiments and D-efficiency of over 85.4 finding the most significant process parameters impacting the etch result. All experiments were carried out for three different via diameters. The evaluation of the via etching was performed using confocal microscopy and by cross sections of the SiC vias. Afterwards the model was verified with etching experiments show very good match with the prediction model. The deviation between the model and the verification was below 6%.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"57 1","pages":"10-13"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83571571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wafer Level Fine-Pitch Hybrid Bonding: Challenges and Remedies 晶圆级细间距杂化键合:挑战与补救
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315002
V. Chidambaram, Yew Wing Leong, Qin Ren
{"title":"Wafer Level Fine-Pitch Hybrid Bonding: Challenges and Remedies","authors":"V. Chidambaram, Yew Wing Leong, Qin Ren","doi":"10.1109/EPTC50525.2020.9315002","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315002","url":null,"abstract":"Fine-pith hybrid bonding has been demonstrated using 3μm Cu pad size and 6μm pitch. TEOS SiO2 is used as a dielectric material. Oxide films were characterized in terms of porosities. A good correlation has been established between the % of porosity in the oxide film and the bonding energy. Chemical-mechanical polishing (CMP) process control challenges in order to achieve a narrow Cu dishing range has also been discussed. It has been recommended that the post-bond annealing temperature needs to be appropriately adjusted in order to achieve good diffusion bonding at the Cu-Cu interface and at the same time mitigate generation of peeling stresses. Disparity in misalignment is observed within the same bonded wafer. To resolve this, a novel solution of designing mating Cu pads of different dimensions is being proposed. Through this design approach, misalignment could be successfully offset and better Cu pad connectivity could be achieved.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"459-463"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83503640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging 芯片封装中逻辑对逻辑和HBM互连模型信号完整性性能评估的频域方法
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315036
Li Kangrong, M. D. Rotaru
{"title":"Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging","authors":"Li Kangrong, M. D. Rotaru","doi":"10.1109/EPTC50525.2020.9315036","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315036","url":null,"abstract":"A novel methodology to evaluate the signal integrity (SI) performance of logic to logic and high bandwidth memory (HBM) interconnect model for chiplet packaging is proposed. Compared with the traditional S parameters and eye diagram analyses, the proposed methodology reflects the actual SI performance under the capacitive termination condition, takes much shorter simulation time and provides more insightful SI evaluation, which is suitable for logic to logic and HBM interconnect design and optimization. The S parameters analysis are not sufficient for the cases like logic to logic and HBM interconnect models, which are unterminated (capacitive loading). The eye diagram analysis cannot provide an insightful guideline for optimization of interconnect model. Besides, eye diagram simulations to find the optimum interconnect model are very time consuming, as a frequency domain to time domain via an inverse fast Fourier transformation (FFT) is required. Compared with the eye diagram analysis, the proposed methodology only analyses the SI performance in frequency domain rather than in time domain, so the simulation time is reduced. The proposed methodology can overcome the drawbacks of the S parameters and eye diagram analyses and provide an in-depth and fast evaluation on the SI performance of logic to logic and HBM interconnect models frequently encountered in advanced system in package using chiplets.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"100 1","pages":"147-151"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84267022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power Module on Copper Lead Frame with Novel Sintering Paste and SnSb solder 新型烧结浆料和SnSb焊料的铜引线框架电源模块
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315011
L. Wai, Kazunori Yamamoto, Simon Lim Siak Boon, T. Yue
{"title":"Power Module on Copper Lead Frame with Novel Sintering Paste and SnSb solder","authors":"L. Wai, Kazunori Yamamoto, Simon Lim Siak Boon, T. Yue","doi":"10.1109/EPTC50525.2020.9315011","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315011","url":null,"abstract":"Die attach and interconnect materials for power module device studied in this experiment included pressure-less sintering paste and SnSb solder. The initial evaluation on various pressure-less silver (Ag) sintering die attach pastes showed that type A paste doesn't form the void after cure, type B with void seen and type C paste has vertical vein likes void seen after oven cure. During copper clip attachment, undesired interconnect seen which caused short circuit between gate and source pads. The proper control during clip attachment was carried out, a good interconnect joint formation without short circuit between gate and source pads was achieved for both pressure-less Ag sintering paste and SnSb solder. Flux cleaning process assisted in removing flux residual on the SnSb reflowed samples.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"115 1","pages":"302-306"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77965666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The Effect of Strip Argon Plasma Cleaning onto the PPF and Ag-plated Cu Leadframe Surfaces 带状氩等离子体清洗对PPF和镀银铜引线架表面的影响
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315017
Matthew M. Fernandez, Marty Lorgino D. Pulutan, A. Arano
{"title":"The Effect of Strip Argon Plasma Cleaning onto the PPF and Ag-plated Cu Leadframe Surfaces","authors":"Matthew M. Fernandez, Marty Lorgino D. Pulutan, A. Arano","doi":"10.1109/EPTC50525.2020.9315017","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315017","url":null,"abstract":"The effect of plasma power and plasma time parameters on the PPF and Ag-plated surfaces were successfully evaluated through surface characterization and leakage functional test. Surface characterization showed that the hydrophobic surface of PPF-plated and Ag-plated leadframes transformed into hydrophilic surface after application of different levels of plasma power and time which is an indication of improvement on wettability. Surface roughness showed that long exposure time can trigger further roughening of the PPF surface. Statistical analysis suggest that the plasma parameters should be kept at leg 6 (mid power, low time). Furthermore, leakage performance of the device showed that increasing the plasma time parameter affect the current leakage performance. Extreme conditions of plasma setting can result to re-deposition of unwanted elements on top of die due to over-etching. The recommended plasma parameter setting showed well-centered current distribution and zero occurrence of leakage failure.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"98 1","pages":"127-129"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80684218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
900 MHz ISM Band RF Energy Harvester for Powering ZigBee Module 用于ZigBee模块供电的900 MHz ISM频段射频能量采集器
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315076
M. Mansour, Shuya Yamamoto, M. Murakami, H. Kanaya
{"title":"900 MHz ISM Band RF Energy Harvester for Powering ZigBee Module","authors":"M. Mansour, Shuya Yamamoto, M. Murakami, H. Kanaya","doi":"10.1109/EPTC50525.2020.9315076","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315076","url":null,"abstract":"ZigBee wireless communication is used for data transmission between two entities. The power consumption of the unit might fall below a few mW. This energy can be provided by using the RF energy harvesting to wirelessly charge a supercapacitor mounted along with the device architecture. The proposed research work offers a significant solution for the battery replacement and tedious work of the circuit maintenance. A rectenna operating at 920 MHz frequency band is used to charge the supercapacitor with high energy levels that can reach up to a few orders of mW. The harvested energy is rectified by a voltage doubler rectifier configuration. The circuit performance is evaluated, tested, and validated to show the agreement between simulation and measurement data. The system shows that the rectenna can provide at least 3 V for the sustainable operation of the ZigBee module. The connection is programmed to initialize every 5-10 seconds so the supercapacitor can re-charge back to the full capacity. The circuit is experimentally tested for continuous operation in a real environment for more than 24 hours.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"74 1","pages":"156-158"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83217523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Thermoelectrics in cryogenic cooling 低温冷却中的热电器件
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315047
Avijit Goswami, S. Kanetkar
{"title":"Thermoelectrics in cryogenic cooling","authors":"Avijit Goswami, S. Kanetkar","doi":"10.1109/EPTC50525.2020.9315047","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315047","url":null,"abstract":"A use case for thermoelectric coolers (TEC) in cryogenic cooling application is presented where the heat load is small and the required temperature difference between the hot and cold sides ($Delta mathrm{T}$) is very high. The application shown here is the cooling of image sensors used in telescopes. These sensors need to be cooled to below −90C (to improve signal to noise ratio) with a heat load of less than 1W at an ambient temperature of $20mathrm{C}$. This has been traditionally done using liquid nitrogen, however, this method requires high maintenance in having to periodically refill nitrogen. A TEC-based solution can offer a significant benefit in terms of lower cost and maintenance. A multi-stage TEC is generally well suited for applications which require a large $Delta mathrm{T}$ and low heat load. In order to determine if a commercially available multistage TEC is enough to meet the $Delta mathrm{T}$ requirement, an experimental setup was created using a vacuum chamber containing TECs inside and a liquid cooling plate on the bottom to remove the heat load from the hot side. Different types of TEC stacks were tested under an applied heat load of 0.6W on the cold side. It was found that although there are many commercially available multi-stage TECs for cryogenic applications, it alone is not enough to achieve the required $Delta mathrm{T}$ of 110C. Also, adding more than 4 or 5 stages to the multistage TEC is not very effective due to the very low COP and the exponential rise of heat dissipation in the lower stages. The maximum $Delta mathrm{T}$ that can be achieved by one multi-stage TEC was found to be only around 90C at a heat load of 0.6W. It is shown here that in order to overcome the $Delta mathrm{T}$ shortfall, an additional layer of 3 single-stage TECs (in parallel) needs to be added at the bottom of the multi-stage TEC in order to increase the total $Delta mathrm{T}$ closer to the required value (110C).","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"355-358"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88271596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Numerical analysis of a MEMS sensor's deformation behavior considering dynamic moisture conditions 动态湿度条件下MEMS传感器变形特性的数值分析
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315091
Mahesh Yalagach, P. Fuchs, T. Antretter, Tao Qi, Markus Weber
{"title":"Numerical analysis of a MEMS sensor's deformation behavior considering dynamic moisture conditions","authors":"Mahesh Yalagach, P. Fuchs, T. Antretter, Tao Qi, Markus Weber","doi":"10.1109/EPTC50525.2020.9315091","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315091","url":null,"abstract":"Micro Electro Mechanical Semiconductors (MEMS) functionalities have been continuously extended during the last years, and they are applied in a wide range of industrial sectors, including the automotive, consumer electronics, and Internet of Things (IoT) markets. These MEMS sensor packages are a multi-materials composite system. The composite materials involved in MEMS sensor packages show significant effects like thermal expansion and hygroscopic swelling when exposed to environmental loads like temperature and moisture. Due to these effects, the MEMS sensing performance is affected. To understand the effects on sensing performance and mechanical behavior, an advanced simulation approach, “hygro-thermo-mechanical simulation,” needs to be accounted for. This approach considers not only the dynamic changes in temperature and moisture loads but also generalized solubility, which is a function of both temperature and saturated mass concentration. This numerical model helps in optimizing and understanding the sensing performance of the MEMS sensor packages.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"12 1","pages":"380-385"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83923168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Washability of Flexible Printed Circuitry for Wearable Electronics Applications 可穿戴电子应用中柔性印刷电路的可洗性
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315138
B. Salam, G. Soo, X. Shan, B. Lok
{"title":"Washability of Flexible Printed Circuitry for Wearable Electronics Applications","authors":"B. Salam, G. Soo, X. Shan, B. Lok","doi":"10.1109/EPTC50525.2020.9315138","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315138","url":null,"abstract":"Wearable electronics are predicted to be 60 billion dollars market by 2024, according to the recent 2020 International Data Corporation (IDC) news. Textile substrates are typically porous and hence the fabrication of electronic circuitry is by heat-transferred which initially was printed on a non-porous substrate such as heat transfer polymer (HTP). Such a fabrication process paved the way for developing new smart clothes. However, most of the developed smart wear clothes are still not practical as they cannot be washed. Therefore, in this study, the effect of the washing, such as water immersion and mechanical stress/bending, towards printed circuitries will be investigated. The test vehicles are silver and carbon circuitries on HTP-polyester and polyethylene terephthalate (PET)-based substrates. The test vehicle on PET serves as a reference. The test vehicles include printed heater patches. The heater patch consists of printed carbon in a rectangle shape and printed silver lines on the two sides. The resistance values of the circuitries were monitored before and after twisted and immersed in water. The results indicate that the effect of water immersion is significant. The resistive value in water could increase up to 12% and 2% for HTP and PET-based test vehicles, respectively. However, the increase in resistance is temporary.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"207-209"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88873045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electrical characterization and design of hyper-dense interconnect on HD-FOWLP for die to die connectivity for AI and ML accelerator applications 用于AI和ML加速器应用的模具间连接的HD-FOWLP上高密度互连的电气特性和设计
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315178
M. D. Rotaru, Li Kangrong
{"title":"Electrical characterization and design of hyper-dense interconnect on HD-FOWLP for die to die connectivity for AI and ML accelerator applications","authors":"M. D. Rotaru, Li Kangrong","doi":"10.1109/EPTC50525.2020.9315178","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315178","url":null,"abstract":"High Density Fan Out Wafer Level Package (HD-FOWLP) can be an alternative for technologies such as Embedded Multi-Die Interconnect Bridge (EMIB) and silicon interposer to achieve heterogeneous integration for applications that requires ultra-high bandwidth for die to die communications. This work focusses on the electrical characteristics of this type of interconnect and explains why the metrics based on S-parameters regularly used for designing and qualifying interconnects on substrates and PCBs are not enough and may be misleading in this case. With the lines cross-sectional dimensions of, 1umx1um and respectively and Nyquist frequency around 1GHz, some of these lines operate at the onset of skin effect, with per-unit-length resistance and inductance undergoing severe dispersion. This is very different from signals routed as thicker and wider traces on an organic package, where the skin effect develops at much lower frequencies. It is also different from the on-die signal routing, where RC is an adequate model of the signal interconnect. Simulation examples of different interconnect structures and layouts are presented to support the findings reported here.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"430-434"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90245574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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