Frequency Domain Methodology for Evaluating Signal Integrity Performance of Logic to Logic and HBM Interconnect Models for Chiplet Packaging

A novel methodology to evaluate the signal integrity (SI) performance of logic to logic and high bandwidth memory (HBM) interconnect model for chiplet packaging is proposed. Compared with the traditional S parameters and eye diagram analyses, the proposed methodology reflects the actual SI performance under the capacitive termination condition, takes much shorter simulation time and provides more insightful SI evaluation, which is suitable for logic to logic and HBM interconnect design and optimization. The S parameters analysis are not sufficient for the cases like logic to logic and HBM interconnect models, which are unterminated (capacitive loading). The eye diagram analysis cannot provide an insightful guideline for optimization of interconnect model. Besides, eye diagram simulations to find the optimum interconnect model are very time consuming, as a frequency domain to time domain via an inverse fast Fourier transformation (FFT) is required. Compared with the eye diagram analysis, the proposed methodology only analyses the SI performance in frequency domain rather than in time domain, so the simulation time is reduced. The proposed methodology can overcome the drawbacks of the S parameters and eye diagram analyses and provide an in-depth and fast evaluation on the SI performance of logic to logic and HBM interconnect models frequently encountered in advanced system in package using chiplets.