Fan-Out Packaging with Thin-film Inductors

Soh Siew Boon, H. Wee, Simon Lim Siak Boon, Sharon Lim Pei Siang, R. Singh, S. Raju
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引用次数: 1

Abstract

Fan-out Wafer Level Packaging is widely and commonly adopted to ease implementation for low-cost packaging. It offers an enhanced solution of standard wafer-level packaging (WLP), which gained popularity for its application in embedding integrated circuitry into smaller packaging approaches. This development involves the study of voltage regulators using an integrated thin-film inductor technology with a laminated magnetic core. Voltage regulators are essential devices in microprocessors, systems-on-chip, and other electronic components to maintain the consistency in the desired operating voltage for the circuits. The inductors and regulators can be co-optimized for achieving good electrical performance. For demonstrating the FOWLP integration of the voltage regulator, the thin-film inductors are embedded into a Fan-out package along with the CMOS controller ASIC. The packaging solution targets to provide high-efficiency power conversion. The electrical characterization results indicated that the low-loss inductor with a peak quality factor of 21 is useful in high-efficiency power conversion.
薄膜电感的扇出封装
扇形晶圆级封装被广泛和普遍采用,以简化低成本封装的实施。它提供了标准晶圆级封装(WLP)的增强解决方案,该解决方案因其在将集成电路嵌入较小封装方法中的应用而受到欢迎。这一发展涉及到使用带有层压磁芯的集成薄膜电感技术来研究电压调节器。稳压器是微处理器、片上系统和其他电子元件中保持电路所需工作电压一致性的基本设备。电感器和稳压器可以协同优化以获得良好的电气性能。为了演示电压调节器的FOWLP集成,薄膜电感器与CMOS控制器ASIC一起嵌入扇出封装中。封装解决方案的目标是提供高效率的电源转换。电学表征结果表明,该低损耗电感的峰值品质因数为21,可用于高效率的功率转换。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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