Strain Response of a Semiconductor Package during Drop Test and Fast Gating Method by Bend Test

Abstract

Board level drop test was widely implemented for solder joint reliability in assembly industry, solder joint was monitored by daisy chain design and real time electrical resistant monitoring to estimate joint life since solder joint failures is the major concern in tradition. In this study, encapsulation molding compound and die crack are the observation points during drop test which is difficult to be detected real-time. Strain analysis of an electronic package during board level drop test were investigated by different levels of JEDEC drop under various drop environments. Taking drop test with 1500G/0.5ms as an example, board strain is around at center of the board area and nearby standoff of a 8 layers daisy-chain board. Meanwhile, package strain on compound side is around 600ue on a package. Main observation is package behaving as bending and the maximum axial strain is approximately 20% to 25% of board strain, both of tensile and compress. As a result, die and encapsulation have potential risks to crack induced by the bending behavior during drop shock testing.