Challenges in Placement Requirements for Heterogeneous Integration

Abstract

The growth of advance packaging especially with Heterogeneous integration and 3D stacking, starting with EMIB (Embedded Multi-die Interconnect Bridge), inFO and CoWoS (Chip-on-Wafer-on-Substrate), Foveros, SoIC (System-on-Integrated Chips) and (3D Multi-Stack) technologies, are emerging as a more cost-efficient way to achieve greater integration and IO densities. With this trend of heterogeneous integration, we can overcome Moore's law and the reliance of few key logic companies with fab capabilities below 7nm or fine pitch packaging. This paper will discuss the impact of challenges to the placement technologies and requirements on SIP in Embedded packaging.