Enhanced Loop Height Optimization for Complex Configuration on QFN Device

Abstract

Wirebonding is one important and critical assembly process in semiconductor packaging responsible for providing electrical connections between the Silicon die and the external leads of the device. The process also brings along manufacturing challenges as the device becomes critical and complex. This paper is focused on the loop height optimization of a Quad-Flat No-leads (QFN) product due to its out of specification reading of less than $10\ \mu\mathrm{m}$ versus the actual minimum specification of $20\ \mu \mathrm{m}$. Comprehensive wire loop optimization and characterization focused on the kink height parameter was done and a wirebonding configuration solution was formulated. Ultimately, the solution prevented low loop reject of wire that could touch or short-circuit with the die. Results revealed a significant improvement in the bump loop height with average measurement of $33\ \mu\mathrm{m}$, conforming to the $20\ \mu\mathrm{m}$ minimum specification. For future works, the configuration could be employed on packages with comparable construction and requirement.