2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)最新文献

筛选
英文 中文
Double Mold Antenna in Package for 77 GHz Automotive Radar 77 GHz汽车雷达双模封装天线
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315071
S. W. Ho, Soh Siew Boon, Lau Boon Long, Hsiao Hsiang-Yao, C. Choong, Sharon Lim Pei Siang, Lim Teck Guan, C. T. Chong
{"title":"Double Mold Antenna in Package for 77 GHz Automotive Radar","authors":"S. W. Ho, Soh Siew Boon, Lau Boon Long, Hsiao Hsiang-Yao, C. Choong, Sharon Lim Pei Siang, Lim Teck Guan, C. T. Chong","doi":"10.1109/EPTC50525.2020.9315071","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315071","url":null,"abstract":"A Fan-out wafer level package (FO-WLP) based Antenna in Package (AiP) test vehicle designed for 77 GHz have been demonstrated in this work. The AiP test vehicle is based on a double mold structure with 4 layers of redistribution lines. The RF device chips are embedded in the bottom mold compound layer, and the antenna arrays are fabricated on the top mold compound layer. This double mold structure was designed to reduce the form factor of AiP as the antenna arrays are fabricated directly on the top mold compound. The antenna structures were designed to meet a design target values of ∼12dBi gain and electrical simulation shows good electrical performance and radiation patterns over 77 to 81 GHz. Finally, the AiP test vehicles were fabricated using the “chip-first” process flow.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"257-261"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77258975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Glass Substrate Interposer for TSV-integrated Surface Electrode Ion Trap 用于tsv集成表面电极离子阱的玻璃衬底中间体
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315003
P. Zhao, Hong Yu Li, Y. Lim, J. Tao, W. Seit, L. Guidoni, C. S. Tan
{"title":"Glass Substrate Interposer for TSV-integrated Surface Electrode Ion Trap","authors":"P. Zhao, Hong Yu Li, Y. Lim, J. Tao, W. Seit, L. Guidoni, C. S. Tan","doi":"10.1109/EPTC50525.2020.9315003","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315003","url":null,"abstract":"To facilitate large-scale implementation of quantum information processing (QIP) based on ion trap system, the design of through silicon via (TSV) integrated ion trap with glass interposer is proposed. Glass interposer is employed for TSV landing and to provide another degree of freedom for electrical signal delivery by the redistribution layer (RDL) on it. Benefited from the insulating property of glass, the parasitic capacitance between electrodes of glass interposer (0.4 pF) is significantly reduced, as compared to its silicon counterparts (650 pF). From the modeling, it is also shown that the reflection loss can be reduced by more than 30 dB when the silicon interposer is replaced by glass interposer. High power efficiency and low heat dissipation can thus be guaranteed during ion trapping operation.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"130 1","pages":"262-265"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88773374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Water balance optimization in hybrid microfluidic cooler embedded in Silicon interposer for data center application 应用于数据中心的嵌入式硅中间层混合微流控冷却器的水平衡优化
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315095
Haoran Chen, Yong Han, G. Tang, Xiaowu Zhang
{"title":"Water balance optimization in hybrid microfluidic cooler embedded in Silicon interposer for data center application","authors":"Haoran Chen, Yong Han, G. Tang, Xiaowu Zhang","doi":"10.1109/EPTC50525.2020.9315095","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315095","url":null,"abstract":"Direct liquid cooling module in thin form factor, or cold plate, greatly improves the capacity and efficiency for high thermal designed power (TDP) processors in modern data centers. To meet the overall cooling demand, previous generation micro-scaled channels, fins, jets and many more fine-structures has been developed. The current generation liquid-cooled cold plates are pursuing better cooling distribution both spatially and temporally, e.g. issues of uniformity, hot-spot and dynamic cooling. While most of the approaches focus on steady-state spatial flow distribution, dynamic adjustable approaches that provide ultimate flexibility of cooling fluid distribution are rare. In the present study, an active flow distribution control algorithm based on piezoelectric micro-valve embedded in a manifold of jet impingement micro-fluidic cooling package will be introduced for non-uniform and dynamic thermal management, especially for integrated 2.5D/3D IC package in data centers for high-performance computing and big-data applications. This study targets on managing and balance of the coolant mass flow distribution across branches of the manifold, to prevent local over-heat in maximum coolant and energy efficiency. Novelties include: 1) a method of active fluid management and balance in micro-channel liquid cooling systems; 2) a directed graph structure for modelling and simulating electronics liquid cooling systems; 3) a controller for the advanced liquid cooling system in data centers.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"365-368"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84460281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Development of micro energy harvest circuit using RF signal 基于射频信号的微能量采集电路的研制
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315008
Ataru Nakashima, M. Mansour, Shunsuke Hatanaka, Osamu Takiguchi, H. Kanaya
{"title":"Development of micro energy harvest circuit using RF signal","authors":"Ataru Nakashima, M. Mansour, Shunsuke Hatanaka, Osamu Takiguchi, H. Kanaya","doi":"10.1109/EPTC50525.2020.9315008","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315008","url":null,"abstract":"This paper presents the design of the micro energy harvesting circuit (MEH) for sensor network systems by using radio wireless waves for wireless telecommunication system. A series L and C resonance circuit is connected in front of the RF-to-DC converting circuit in our proposed circuit in order to enhance the radio frequency (RF) signal. RF-to-DC converting circuit is based on the Dickson voltage multiplier and designed the cascode and cascade connection to obtain the high DC output voltage. Surface mount type devices such as diode, capacitor etc. are placed on the differential strip line. In the simulation, cascade structure has more than 2V DC output from 900MHz to 2.4GHz.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"51 1","pages":"152-155"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87600229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the determination of Young's modulus of film by nanoindentation 用纳米压痕法测定薄膜的杨氏模量
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315023
Q. Jia, X. Long
{"title":"On the determination of Young's modulus of film by nanoindentation","authors":"Q. Jia, X. Long","doi":"10.1109/EPTC50525.2020.9315023","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315023","url":null,"abstract":"With the development of miniaturization of electronic chips and their packaging structures, electronic devices are becoming highly integrated. The thickness or area of packaging materials required for device packaging structures is significantly reduced, so that the properties of those small-sized packaging materials cannot be measured using the conventional testing methods. However, for the measurement of Young's modulus of thin film by nanoindentation technology, with the increase of indentation depth, the elastic-plastic deformation of the film and the substrate will change constantly. Therefore, the mechanical property evaluation of the composite is a complex function of the film and substrate's mechanical properties. Based on finite element simulations, the influence of Young's modulus of film and substrate on the mechanical properties of composite materials is studied. The accuracy of Young's modulus calculation of film is verified and summarized by four different weight functions which are used to simulate a variety of film/substrate combinations. At the same time, for the cases with Young's modulus of the film larger or smaller than that of the substrate, the stress distribution and indentation morphology of the film/substrate composite are also discussed. Generally, the substrate modulus is taken as a known parameter in the fitting process. The weight function is applied to a variety of real composite materials to verify the effectiveness of the conclusions drawn by unknow materials.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"114 1","pages":"228-232"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89557829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of Package Pick and Place Process to Induce Chip Crack in Package by Different Stress Modes 不同应力模式下封装取放工艺对封装芯片裂纹的影响
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9314997
Jong-gi Lee, Bo-Sung Kim, Taekyun Kang, Kang-Young Cho
{"title":"Effect of Package Pick and Place Process to Induce Chip Crack in Package by Different Stress Modes","authors":"Jong-gi Lee, Bo-Sung Kim, Taekyun Kang, Kang-Young Cho","doi":"10.1109/EPTC50525.2020.9314997","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9314997","url":null,"abstract":"Due to strong demand for thin profile package in smart phone with higher memory density (more dies in the package), each component in memory package, such as substrate thickness, solder ball height, EMC thickness and gap between top chip and EMC top surface has been reduced to meet required total package thickness. The mechanical point of view, Si chip has the highest modulus and more prone to defect by external stress. In this paper, possible stress modes to create chip crack during pick and place process during SMT and the best combination of pick and place process for thin multi-chip package were investigated and provided meaningful process parameters for available pick and place models","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"495 1","pages":"101-103"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83857659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Board Level Solder Joint Reliability Design and Analysis of FOWLP FOWLP板级焊点可靠性设计与分析
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9314996
Xiaowu Zhang, B. L. Lau, Haoran Chen, Yong Han, M. C. Jong, S. Lim, S. Lim, Xiaobai Wang, Y. Andriani, Songlin Liu
{"title":"Board Level Solder Joint Reliability Design and Analysis of FOWLP","authors":"Xiaowu Zhang, B. L. Lau, Haoran Chen, Yong Han, M. C. Jong, S. Lim, S. Lim, Xiaobai Wang, Y. Andriani, Songlin Liu","doi":"10.1109/EPTC50525.2020.9314996","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9314996","url":null,"abstract":"This paper presents a comprehensive board level solder joint reliability study under thermal cycling (TC) loading by both numerical simulation and experimental test. TC profile is from −40°C to 125°C. In numerical simulation, both epoxy molding compound (EMC) and dielectric are modeled as viscoelastic materials. SAC is modeled as a creep material while the remaining materials are assumed to be elastic. The critical solder joint location predicted by modeling agrees well with the experimental result. Results show: (1) lower CTE PCB improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB CTE is reduced from 17 ppm/°C to 10ppm/°C; (2) thinned PCB thickness improves the board level solder joint fatigue life as creep strain energy density range of solder joint is reduced when PCB thickness is reduced from 1.5 mm to 1 mm. Finally, life prediction model for solder joints of FOWLP has been successfully established as well.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"78 1","pages":"316-320"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83935195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hybrid 3D Package with RDL and Laminate Substrate for Ultra-Thin and High-Bandwidth Applications 混合3D封装与RDL和层压板的超薄和高带宽应用
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315082
Jaeyoon Kim, Kyeryung Kim, Eunyoung Lee, S. Hong, JuHong Shin, MinKeon Lee, Ji Hun Lee, David Hiner, Wonchul Do
{"title":"Hybrid 3D Package with RDL and Laminate Substrate for Ultra-Thin and High-Bandwidth Applications","authors":"Jaeyoon Kim, Kyeryung Kim, Eunyoung Lee, S. Hong, JuHong Shin, MinKeon Lee, Ji Hun Lee, David Hiner, Wonchul Do","doi":"10.1109/EPTC50525.2020.9315082","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315082","url":null,"abstract":"In this work, a hybrid 3D package combining a redistribution layer (RDL) and laminate substrate layer for ultra-thin and high-bandwidth mobile applications are discussed and demonstrated. The motivation behind this hybrid 3D package structure was leveraging the advantages of high density RDL layer and advanced laminate substrate layer in one package to optimize package features or performance in bandwidth, package height, assembly manufacturing and package level as well as board level reliability to each specific industry requirement. For demonstration purposes, a $12.5times 12.5-text{mm}$ hybrid 3D packages combining a high density RDL and advanced laminate-substrate layer were designed and manufactured. In this demonstration, the $12.5times 12.5-text{mm}$ hybrid 3D package showed $395 mu mathrm{m}$ package height including ball grid array (BGA) solder ball height and package warpage of $+64 mu mathrm{m}$ (in crying mode) at 25°C and $-81 mu mathrm{m}$ (in smile mode) at 260°C. The demonstration package passed package level reliability tests including unbiased highly accelerated stress test (uHAST), temperature cycling (TC) test and high temperature storage (HTS) test. The package showed less creep strain energy density (CSED) of the BGA solder balls under board level reliability-temperature cycling conditions than that of the RDL-based 3D package in the finite element model (FEM) simulation to a fully top package and 3D package stacked structure.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"66 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84980636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Predictive Solder Joint Reliability Modeling for Early Risk Assessment 用于早期风险评估的预测焊点可靠性建模
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315056
K. Sinha, Christopher D. Glancey, H. Takiar, Yeow Chon Ong, L. Pan
{"title":"Predictive Solder Joint Reliability Modeling for Early Risk Assessment","authors":"K. Sinha, Christopher D. Glancey, H. Takiar, Yeow Chon Ong, L. Pan","doi":"10.1109/EPTC50525.2020.9315056","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315056","url":null,"abstract":"The reliability of electronic product is a very important concern for customer and product users. These electronic packages are susceptible to solder joint failure arising from CTE mismatch and thermo-mechanical stresses during thermal cycling conditions. Hence, methods to improve and predict the service life of electronic packages are important challenges for on-going research on design for reliability. A robust and accurate life prediction model [1] is an effective engineering tool to accurately predict fatigue life of the package within a short time without resorting to perform expensive and time-consuming reliability life data collection. However, the life prediction accuracy of finite element simulation models is dependent on modeling assumptions, geometrical complexity, creep constitutive model of solder and fatigue life model calculation [2]–[8]. This paper examines how the accuracy of life prediction model is established by correlating the reliability test data with predicted SED (strain energy density) values in the simulation models (Fig. 2). The optimized life prediction model is verified with the measured reliability data of different packages for its accuracy. Given that solder joint failure is one of the major electrical failures during thermal cycling testing, it is imperative to establish an accurate life prediction model (Fig. 3) and understand how different package designs and material selection affect the solder joint integrity. Based on the finite element analysis, the resulting simulation findings will add insight in enhancing solder joint reliability against thermo-mechanical loading. Early risk assessment can also be performed to identify high-risk design which requires immediate attention as well as low-risk design which can be assessed to proceed with reduced qualification plan.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"330-334"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83544241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Application of Face-Centered Central Composite Design for the Optimization of Chemical Etching Process of QFN-mr Package Using Alkaline-Based Chemical Solution 面心中心复合设计在QFN-mr封装碱性化学溶液化学蚀刻工艺优化中的应用
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC) Pub Date : 2020-12-02 DOI: 10.1109/EPTC50525.2020.9315087
Rohn Kenneth L. Serapio, Ernesto T. Antilano, Alvin S. Soreda
{"title":"Application of Face-Centered Central Composite Design for the Optimization of Chemical Etching Process of QFN-mr Package Using Alkaline-Based Chemical Solution","authors":"Rohn Kenneth L. Serapio, Ernesto T. Antilano, Alvin S. Soreda","doi":"10.1109/EPTC50525.2020.9315087","DOIUrl":"https://doi.org/10.1109/EPTC50525.2020.9315087","url":null,"abstract":"Quad-Flat No Lead Multi-row (QFN-mr) is a common type of integrated circuit (IC) package that is leadless and plastically encapsulated in build. Before being cut into units through singulation process, QFN-mr packages are in Cu leadframe strip form and typically subjected to chemical wet etching treatment to remove Cu metal in areas between lead and pad and eventually, prevent metal shorting issue during soldering of individual units. The objective of this work is to establish optimum parameter combination for the chemical etching of QFN-mr package using face-centered central composite design as experimental design and alkaline-based solution as chemical etching agent. Experimental runs were carried out in a conveyorized, horizontal wet etching line. From the results, it was found out that the amount of material etched increases as conveyor speed and etching nozzle spray pressure are decreased and increased, respectively. Optimum setting was predicted to be at 55 cm/min conveyor speed and 1.67 bar etching spray pressure. This produced the target lead and pad dimensional response, as proved by the results of the actual confirmatory test performed.","PeriodicalId":6790,"journal":{"name":"2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)","volume":"1999 1","pages":"413-418"},"PeriodicalIF":0.0,"publicationDate":"2020-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88285782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信