Effect of Package Pick and Place Process to Induce Chip Crack in Package by Different Stress Modes

Abstract

Due to strong demand for thin profile package in smart phone with higher memory density (more dies in the package), each component in memory package, such as substrate thickness, solder ball height, EMC thickness and gap between top chip and EMC top surface has been reduced to meet required total package thickness. The mechanical point of view, Si chip has the highest modulus and more prone to defect by external stress. In this paper, possible stress modes to create chip crack during pick and place process during SMT and the best combination of pick and place process for thin multi-chip package were investigated and provided meaningful process parameters for available pick and place models