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2015 IEEE Custom Integrated Circuits Conference (CICC)最新文献

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Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology 自定义6-R, 2-或4-W多端口寄存器文件，在ASIC SOC中，DVFS窗口为0.5 V, 130 MHz至0.96 V, 3.2 GHz，采用28nm HKMG CMOS技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338445
H. Hsieh, S. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, P. Yang, Kevin Huang, Min-Jer Wang, W. Hwang
{"title":"Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology","authors":"H. Hsieh, S. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, P. Yang, Kevin Huang, Min-Jer Wang, W. Hwang","doi":"10.1109/CICC.2015.7338445","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338445","url":null,"abstract":"We describe custom 6R, 2/4W general-purpose register files (GRF) in an ASIC-based SOC implemented in a N28 CMOS technology, which has roughly a 2~3 X smaller area, 2 X faster speed, and 5 X lower power than a logic-synthesized version. Synthesized and custom GRFs also have a different read behavior from static and dynamic circuitry used, respectively. This is addressed by modifying a bypass control block. Hardware showed a DVFS window of 0.5 V @circuit, 130 MHz to 0.96 V, 3.2 GHz.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"77 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77461430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT 在0.25 um GaN HEMT中实现200 ms /s 98 db信噪比跟踪保持
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338405
SungWon Chung, Hae-Seung Lee
{"title":"A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT","authors":"SungWon Chung, Hae-Seung Lee","doi":"10.1109/CICC.2015.7338405","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338405","url":null,"abstract":"In order to overcome the design challenges of GaN HEMT leakage and Schottky diode turn-on, a GaN track-and-hold (T/H) circuit with 20-V pseudo-differential input swing consists of an asymmetric gate device followed by a symmetric gate device. The GaN T/H provides 98-dB SNR at 200 MS/s while drawing 195 mA.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"24 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73865242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A few behavioral modeling options for balancing verification coverage and credibility 一些用于平衡验证覆盖率和可信度的行为建模选项
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338436
J. Chen
{"title":"A few behavioral modeling options for balancing verification coverage and credibility","authors":"J. Chen","doi":"10.1109/CICC.2015.7338436","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338436","url":null,"abstract":"• The purpose of verification is to reduce the risk of silicon not meeting performance specifications or worse yet, not functioning. Since the silicon does not yet exist, verification depends on simulations. Simulations in turn depend on models. In verification terms, the classical modeling tradeoff between speed and accuracy translates into a tradeoff between test coverage and model credibility (or validity). Transistor- eve models produce the most credible simulations but slow run times and convergence problems severely limit test coverage. At the other extreme, a high level flat model quickly simulates all required tests but is least credible because the high level of abstraction greatly increases the chances for un-modeled circuit bugs and other relevant omitted behaviors. A “good” modeling boundary balances coverage and credibility. The balance is subjective because it depends on schedule, available resources, and acceptable risk. Given how strongly verification depends on the overall modeling strategy, it helps to have as many modeling options as possible. This tutorial describes a few modeling methods to balance coverage and credibility.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"93 1","pages":"1-115"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80316631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited) FinFET技术在先进节点上的扩展挑战及其对SoC设计的影响(特邀)
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338378
S. Banna
{"title":"Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited)","authors":"S. Banna","doi":"10.1109/CICC.2015.7338378","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338378","url":null,"abstract":"With the introduction of FinFET technology in mass production, more designs and complex designs are being ported on 22nm and 14nm/16nm FinFET transistors. However, all FinFET transistors are not made equal to offer best System-on-Chip (SoC) performance and power benefits. Careful selection of fin structural parameters is critical for best SoC performance. This paper discusses FinFET scaling challenges, their impact on SoC performance, key trade-offs and possible solutions for best SoC performance at current and future technology nodes.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"105 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86486556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 16-channel, 1-second latency patient-specific seizure onset and termination detection processor with dual detector architecture and digital hysteresis 一个16通道，1秒延迟患者特定的癫痫发作和终止检测处理器，具有双检测器架构和数字滞后
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338458
Chen Zhang, Muhammad Awais Bin Altaf, Jerald Yoo
{"title":"A 16-channel, 1-second latency patient-specific seizure onset and termination detection processor with dual detector architecture and digital hysteresis","authors":"Chen Zhang, Muhammad Awais Bin Altaf, Jerald Yoo","doi":"10.1109/CICC.2015.7338458","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338458","url":null,"abstract":"This paper presents an area-power-efficient 16-channel seizure onset and termination detection processor with patient-specific machine learning techniques. This is the first work in literature to report an on-chip classification to detect both start and end of seizure event simultaneously with high accuracy. Frequency-Time Division Multiplexing (FTDM) filter architecture and Dual-Detector Architecture (D2A) is proposed, implemented and verified. The D2A incorporates two area-efficient Linear Support Vector Machine (LSVM) classifiers along with digital hysteresis to achieve a high sensitivity and specificity of 95.7% and 98%, respectively, using CHB-MIT EEG database [1], with a small latency of 1s. The overall energy efficiency is measured as 1.85μJ/Classification at 16-channel mode.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"92 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74618807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration 一个1.8 pj /bit 16×16-Gb/s的32nm SOI CMOS源同步并行接口，具有接收器冗余，用于链路重新校准
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338371
T. Dickson, Yong Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, D. Friedman
{"title":"A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration","authors":"T. Dickson, Yong Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, D. Friedman","doi":"10.1109/CICC.2015.7338371","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338371","url":null,"abstract":"A 16×16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on current-integrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75\" traces) and 1.9pJ/bit (10\" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"166 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75640860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS 一种4×20-Gb/s 0.86pJ/b/lane 2-抽头ffe源端串联发射机，具有远端串扰消除和65nm CMOS无分频时钟生成
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338414
S. Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Wen Jia, Chun Zhang, Zhihua Wang
{"title":"A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS","authors":"S. Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Wen Jia, Chun Zhang, Zhihua Wang","doi":"10.1109/CICC.2015.7338414","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338414","url":null,"abstract":"A 4×20-Gb/s source-series-terminate (SST) transmitter with 2-tap FFE and far-end crosstalk (FEXT) cancellation is presented. The FFE and crosstalk canceller (XTC) are merged together with the SST driver. The proposed transmitter architecture with divider-less clock generation can not only guarantee the timing requirement for the highest-speed serialization under PVT variation, but also save a lot of hardware cost and power compared with the conventional designs. Fabricated in a 65-nm CMOS technology, the transmitter achieves a maximum data rate of 20-Gb/s with a power efficiency of 0.86pJ/b/lane. For two 2-inch channels with spacing of 30-mil, the measured total jitter (TJ) of the 20-Gb/s eye diagram is 27.8ps for 1e-12 BER, and the peak-to-peak data dependent jitter (DDJ) is improved by 36.9% due to the XTC.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"90 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75716832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space 83fps 1080P分辨率354mw硅实现，用于计算改进的仿射空间鲁棒特性
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338481
S. Yin, P. Ouyang, Leibo Liu, Shaojun Wei
{"title":"A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space","authors":"S. Yin, P. Ouyang, Leibo Liu, Shaojun Wei","doi":"10.1109/CICC.2015.7338481","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338481","url":null,"abstract":"In comparison with the popular feature algorithms in vision applications, AFFINE-SIFT (ASIFT) achieves the highest robustness in terms of illumination, rotation, and scale in affine space but exhibits high computation complexity. This work proposes three optimization techniques, including reverse based pipelined affine computing, full parallel Gaussian pyramid computing and rotation invariant binary pattern (RIBP) based feature vector computing, to accelerate the computation intensive parts in ASIFT, and design a high efficient pipelined and parallel architecture for the whole ASIFT. Using TSMC 65 nm process, silicon implementation shows that this work achieves the processing speed of 83fps@1080p (1000 feature points per frame on average) with 200 MHz while dissipating 354 mW. It fully supports the real time processing of high resolution images in vision scenes with strong robustness.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"86 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80347504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 30.1μm2, < ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoring 一个30.1μm2， <±1.1°c -3σ-误差，0.4 ~ 1.0 v的基于直接阈值电压传感的温度传感器，用于片上密集热监测
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338397
Seongjong Kim, Mingoo Seok
{"title":"A 30.1μm2, < ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoring","authors":"Seongjong Kim, Mingoo Seok","doi":"10.1109/CICC.2015.7338397","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338397","url":null,"abstract":"This paper presents on-chip temperature sensor circuits for dense thermal monitoring in digital VLSI systems. The sensor directly captures the temperature dependency of threshold voltage. The prototype in a 65nm demonstrates that as compared to the state of the arts it can achieve a 9× smaller footprint of 30.1μm2 and a 3× smaller 3σ-error of <;±1.1°C after one temperature point calibration. The proposed sensor also achieves a 0.2V better voltage scalability than the previous best voltage-scalable design.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79792894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter 一种带宽为4mW、集成抖动为1.9psrms的环形分数n DPLL
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338376
Ahmed Elkholy, Saurabh Saxena, R. Nandwana, A. Elshazly, P. Hanumolu
{"title":"A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter","authors":"Ahmed Elkholy, Saurabh Saxena, R. Nandwana, A. Elshazly, P. Hanumolu","doi":"10.1109/CICC.2015.7338376","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338376","url":null,"abstract":"In this paper, a ring oscillator based fractional-N DPLL that achieves low jitter by extending bandwidth using noise cancellation techniques is presented. A dual-path digital loop filter architecture is employed to resolve the ΔΣ DAC quantization noise challenge. Fabricated in 65nm CMOS process, the proposed PLL operates over a wide frequency range of 4GHz-5.5GHz and achieves 1.9psrms jitter while consuming only 4mW. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNDPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference. The FoM is -228.5dB, which is at least 20dB better than all reported ring-based FNDPLLs.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"34 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85051331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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