A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space

Abstract

In comparison with the popular feature algorithms in vision applications, AFFINE-SIFT (ASIFT) achieves the highest robustness in terms of illumination, rotation, and scale in affine space but exhibits high computation complexity. This work proposes three optimization techniques, including reverse based pipelined affine computing, full parallel Gaussian pyramid computing and rotation invariant binary pattern (RIBP) based feature vector computing, to accelerate the computation intensive parts in ASIFT, and design a high efficient pipelined and parallel architecture for the whole ASIFT. Using TSMC 65 nm process, silicon implementation shows that this work achieves the processing speed of 83fps@1080p (1000 feature points per frame on average) with 200 MHz while dissipating 354 mW. It fully supports the real time processing of high resolution images in vision scenes with strong robustness.