T. Dickson, Yong Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, D. Friedman
{"title":"一个1.8 pj /bit 16×16-Gb/s的32nm SOI CMOS源同步并行接口，具有接收器冗余，用于链路重新校准","authors":"T. Dickson, Yong Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, D. Friedman","doi":"10.1109/CICC.2015.7338371","DOIUrl":null,"url":null,"abstract":"A 16×16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on current-integrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75\" traces) and 1.9pJ/bit (10\" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"166 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration\",\"authors\":\"T. Dickson, Yong Liu, A. Agrawal, J. Bulzacchelli, H. Ainspan, Z. Deniz, B. Parker, M. Meghelli, D. Friedman\",\"doi\":\"10.1109/CICC.2015.7338371\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 16×16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on current-integrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75\\\" traces) and 1.9pJ/bit (10\\\" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.\",\"PeriodicalId\":6665,\"journal\":{\"name\":\"2015 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"166 1\",\"pages\":\"1-4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2015.7338371\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2015.7338371","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
在32nm SOI CMOS中报道了一个16×16-Gb/s源同步I/O。总线级接收器包括冗余RX通道，以减少功率和面积开销，实现通道重新校准。I/O还包括一个具有8相时钟的8:1 TX串行器，以及一个基于有源电感器的RX CTLE，其输出与RX采样器的输入形成电流镜像。描述了一种基于电流积分相位插值器内核的相位旋转器，与现有技术相比，其结构和电路性能有所改进。在Megtron-6走线上进行的16 gb /s链路测量显示，效率为1.8pJ/bit(0.75”走线)和1.9pJ/bit(10”走线)，时间裕度>30%，TX、RX和PLL由1V电源供电。
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration
A 16×16-Gb/s source-synchronous I/O is reported in 32nm SOI CMOS. The bus-level receiver includes redundant RX lanes to enable lane recalibration with reduced power and area overhead. The I/O also includes an 8:1 TX serializer with 8-phase clocking, and an active-inductor-based RX CTLE whose outputs form current mirrors with the inputs of the RX samplers. A phase rotator based on current-integrating phase interpolator cores is described, with architecture and circuit improvements to performance as compared to prior art. 16-Gb/s link measurements over Megtron-6 traces demonstrate efficiencies of 1.8pJ/bit (0.75" traces) and 1.9pJ/bit (10" traces) with >30% timing margin, with the TX, RX, and PLL operating from 1V supplies.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
