H. Hsieh, S. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, P. Yang, Kevin Huang, Min-Jer Wang, W. Hwang
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引用次数: 3
摘要
我们描述了在N28 CMOS技术中实现的基于asic的SOC中的自定义6R, 2/ 4w通用寄存器文件(GRF)，它比逻辑合成版本具有大约2~3倍的面积，2倍的速度和5倍的功耗。合成和自定义grf也分别具有不同于所使用的静态和动态电路的读取行为。这是通过修改旁路控制块来解决的。硬件显示的DVFS窗口为0.5 V @电路，130 MHz至0.96 V, 3.2 GHz。
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology
We describe custom 6R, 2/4W general-purpose register files (GRF) in an ASIC-based SOC implemented in a N28 CMOS technology, which has roughly a 2~3 X smaller area, 2 X faster speed, and 5 X lower power than a logic-synthesized version. Synthesized and custom GRFs also have a different read behavior from static and dynamic circuitry used, respectively. This is addressed by modifying a bypass control block. Hardware showed a DVFS window of 0.5 V @circuit, 130 MHz to 0.96 V, 3.2 GHz.
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