2015 IEEE Custom Integrated Circuits Conference (CICC)最新文献_第10页

An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS 一种基于8通道模拟- fft的450MS/s混合滤波器组ADC，具有改进的SNDR，可用于40nm CMOS的多频段信号

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338459

Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, D. Markovic, R. Harjani

{"title":"An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS","authors":"Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, D. Markovic, R. Harjani","doi":"10.1109/CICC.2015.7338459","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338459","url":null,"abstract":"We present a fully integrated hybrid filter bank ADC based on an analog-FFT geared for baseband signal processing in wireless receivers. The design consists of an 8-point A-FFT for an analysis filter bank, a VGA bank and a sub-ADC bank in the analog domain, and an inverse VGA bank, calibration and inverse FFT for the synthesis filter in the digital domain. The proposed structure enables the signals in each channel of the 450MHz wide band system to be separately digitized using the full dynamic range of the ADC. The prototype is implemented in TSMC's 40nm CMOS GP process. A hybrid filter bank ADC does not have a constant average noise floor and is best used when both large and small signals are present. After calibration, the reconstructed signal with an asymmetric (40dB difference) two tone input, i.e., one large at 1MHz and one small at 225.05MHz shows 55.7dB of image rejection. The SNDR of the smaller signal improves by 6.0dB in comparison to a non-channelized ADC. The total power consumption for both the analog and digital sections is 90.4mW. As far as we are aware this is the first integrated implementation of the full hybrid filter bank principle.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"21 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87563437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A millimeter-wave fully differential transformer-based passive reflective-type phase shifter 基于毫米波全差动变压器的无源反射型移相器

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338423

Tso-Wei Li, Hua Wang

引用次数: 9

A 0.1–5.0GHz self-calibrated SDR transmitter with −62.6dBc CIM3 in 65nm CMOS 一个0.1-5.0GHz自校准SDR发射机，−62.6dBc CIM3, 65nm CMOS

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338452

Yun Yin, Yanqiang Gao, Zhihua Wang, B. Chi

引用次数: 3

Session 6 — Analog circuits using digital cells 第六部分-使用数字单元的模拟电路

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338465

J. Yang, A. Raychowdhury

{"title":"Session 6 — Analog circuits using digital cells","authors":"J. Yang, A. Raychowdhury","doi":"10.1109/CICC.2015.7338465","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338465","url":null,"abstract":"Summary form only given. This session presents state-of-the-art techniques for implementing analog circuits using digital cells and cell library elements. The first paper is an invited paper that discusses design opportunities using inverter based amplifier cells. The authors demonstrate PVT tolerant biasing of inverter based OTAs and validate the theory with experimental data. This is an invited paper in this session. The second paper discussed the design of an 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16× TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL and INL are 1.84LSB and 2.36LSB, respectively. The TDC area is 0.07mm2. This third paper in the session presents a fully synthesized 0.4V analog Biquad filter in a 0.13μm technology using digital standard cells. A reconfigurable multi-state op-amp using has been proposed. The filter is implemented using Verilog code and synthesized using automated place and route. The prototype IC achieves 77.17dB peak SFDR and a tunable bandwidth of 1.7-2.5MHz while consuming 0.8mW power from a 0.4V analog supply and 1V supply for the switches.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"60 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84540729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 550μm2 CMOS temperature sensor using self-discharging P-N diode with ±0.1°C (3σ) calibrated and ±0.5°C (3σ) uncalibrated inaccuracies 采用自放电P-N二极管的550μm2 CMOS温度传感器，校准误差为±0.1°C (3σ)，未校准误差为±0.5°C (3σ)

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-25 DOI: 10.1109/CICC.2015.7338457

Golam R. Chowdhury, A. Hassibi

引用次数: 1

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction 一个10.5 b enob645 nW 100kS/s SAR ADC，基于统计估计降噪

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-25 DOI: 10.1109/CICC.2015.7338493

Long Chen, Xiyuan Tang, A. Sanyal, Yeonam Yoon, Jie Cong, Nan Sun

引用次数: 23

A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0–1 MASH ADC with direct digital background nonlinearity calibration 一个12b ENOB, 2.5MHz-BW, 4.8mW基于vco的0-1 MASH ADC，直接数字背景非线性校准

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-25 DOI: 10.1109/CICC.2015.7338494

Kareem Ragab, Nan Sun

引用次数: 11

A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants 近最佳的13.56 MHz有源整流器与电路延迟实时校准大电流生物医学植入物

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-25 DOI: 10.1109/CICC.2015.7338391

Cheng Huang, T. Kawajiri, H. Ishikuro

引用次数: 7

A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration 一个0.04 mm2 0.9 mw 71 db SNDR分布式模块化AS ADC，具有基于vco的集成商和数字DAC校准

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-25 DOI: 10.1109/CICC.2015.7338461

Yeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun

引用次数: 13

Sub-sampling PLL techniques 分采样锁相环技术

2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-09-28 DOI: 10.1109/CICC.2015.7338420

Xiang Gao, E. Klumperink, B. Nauta

引用次数: 26