A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration

Abstract

This paper presents a low-power and small-area VCO-based closed-loop ΔΣ ADC with two highlights. First, the ADC has a distributed modular architecture. It consists of repetitive slices, which simplifies both schematic and layout design. It allows the ADC to be easily reconfigured for other resolution specifications. Second, a novel digital DAC mismatch calibration technique is proposed. It has low hardware complexity by taking advantage of the intrinsic clocked averaging (CLA) capability of dual VCO-based integrator. It ensures high linearity in the presence of large DAC mismatches. A prototype ADC in 130nm CMOS occupies only 0.04mm2. It achieves 71dB SNDR over 1.7MHz BW while sampling at 250MS/s and consuming 0.9mW under a 1.2V supply.