Session 6 — Analog circuits using digital cells

Abstract

Summary form only given. This session presents state-of-the-art techniques for implementing analog circuits using digital cells and cell library elements. The first paper is an invited paper that discusses design opportunities using inverter based amplifier cells. The authors demonstrate PVT tolerant biasing of inverter based OTAs and validate the theory with experimental data. This is an invited paper in this session. The second paper discussed the design of an 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16× TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL and INL are 1.84LSB and 2.36LSB, respectively. The TDC area is 0.07mm2. This third paper in the session presents a fully synthesized 0.4V analog Biquad filter in a 0.13μm technology using digital standard cells. A reconfigurable multi-state op-amp using has been proposed. The filter is implemented using Verilog code and synthesized using automated place and route. The prototype IC achieves 77.17dB peak SFDR and a tunable bandwidth of 1.7-2.5MHz while consuming 0.8mW power from a 0.4V analog supply and 1V supply for the switches.