A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter

Abstract

In this paper, a ring oscillator based fractional-N DPLL that achieves low jitter by extending bandwidth using noise cancellation techniques is presented. A dual-path digital loop filter architecture is employed to resolve the ΔΣ DAC quantization noise challenge. Fabricated in 65nm CMOS process, the proposed PLL operates over a wide frequency range of 4GHz-5.5GHz and achieves 1.9psrms jitter while consuming only 4mW. The measured in-band phase noise is better than -96 dBc/Hz at 1MHz offset. The proposed FNDPLL achieves wide bandwidth up to 6MHz using a 50 MHz reference. The FoM is -228.5dB, which is at least 20dB better than all reported ring-based FNDPLLs.