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2015 IEEE Custom Integrated Circuits Conference (CICC)最新文献

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A 4.6mW, 22dBm IIP3 all MOSCAP based 34–314MHz tunable continuous time filter in 65nm 一个4.6mW, 22dBm IIP3全MOSCAP基于34-314MHz可调谐连续时间滤波器，65nm
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338402
Rakesh Kumar Palani, R. Harjani
{"title":"A 4.6mW, 22dBm IIP3 all MOSCAP based 34–314MHz tunable continuous time filter in 65nm","authors":"Rakesh Kumar Palani, R. Harjani","doi":"10.1109/CICC.2015.7338402","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338402","url":null,"abstract":"A inverter based filter design is proposed that uses only MOSCAPs as filter capacitors. Further in the design the load capacitance compensates the negative feedback network allowing the majority of current to flow into the load. This results in an increase in the overall power efficiency. As a proof of concept, a 3rd order inverter based 34-314 MHz tunable continuous time channel select filter for software-defined radios is fabricated in TSMCs 65nm technology. By using the high density tunable MOSCAPs at a low swing node, the filter achieves an OIP3 of +25.24 dBm while drawing 4.2mA from a 1.1V supply and occupies an area of 0.007mm2. The measured intermodulation distortion varies by 5dB across a 120° variation in temperature and 6.5dB across a 200mV variation in power supply. Further, the filter presents a high impedance node at the input and a low impedance node at the output easing system integration.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87345432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low dropout regulators 低差稳压器
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338435
P. Hanumolu
{"title":"Low dropout regulators","authors":"P. Hanumolu","doi":"10.1109/CICC.2015.7338435","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338435","url":null,"abstract":"This paper discusses the roles of low dropout regulators.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"4 1","pages":"1-37"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87439769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Embedded cooling technologies for densely integrated electronic systems 用于密集集成电子系统的嵌入式冷却技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338365
Thomas E. Sarvey, Yang Zhang, Li Zheng, Paragkumar Thadesar, R. Gutala, Colman Cheung, Arifur Rahman, M. Bakir
{"title":"Embedded cooling technologies for densely integrated electronic systems","authors":"Thomas E. Sarvey, Yang Zhang, Li Zheng, Paragkumar Thadesar, R. Gutala, Colman Cheung, Arifur Rahman, M. Bakir","doi":"10.1109/CICC.2015.7338365","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338365","url":null,"abstract":"In modern integrated systems, interconnect and thermal management technologies have become two major limitations to system performance. In this paper, a number of technologies are presented to address these challenges. First, low-loss polymer-embedded vias are demonstrated in thick wafers compatible with microfluidics. Next, fluidic I/Os for delivery of fluid to microfluidic heat sinks are demonstrated in assembled 2.5D and 3D stacks. Then thermal coupling between dice in 2.5D and 3D systems is explored. Lastly, the utility of microfluidic cooling is demonstrated through an FPGA, built in a 28nm process, with a monolithically integrated microfluidic heat sink.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87033103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Supply noise induced jitter modeling and optimization for high-speed interfaces 高速接口的电源噪声诱发抖动建模与优化
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338439
D. Oh, Yujeong Shim, Guang Chen
{"title":"Supply noise induced jitter modeling and optimization for high-speed interfaces","authors":"D. Oh, Yujeong Shim, Guang Chen","doi":"10.1109/CICC.2015.7338439","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338439","url":null,"abstract":"• Issues and challenges in power distribution network design • Basics of power supply induced jitter (PSIJ) modeling — Power distribution network (PDN) modeling — Jitter sensitivity function modeling • PSIJ design and modeling for key applications — Memory and parallel bus interfaces — Serial links — Digital logic timing.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"386 1","pages":"1-42"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74276654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
390–640MHz tunable oscillator based on phase interpolation with −120dBc/Hz in-band noise 基于相位插值的390-640MHz可调谐振荡器，带内噪声为- 120dBc/Hz
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338451
Xu Meng, Lianhong Zhou, Fujian Lin, C. Heng
{"title":"390–640MHz tunable oscillator based on phase interpolation with −120dBc/Hz in-band noise","authors":"Xu Meng, Lianhong Zhou, Fujian Lin, C. Heng","doi":"10.1109/CICC.2015.7338451","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338451","url":null,"abstract":"A high frequency tunable oscillator (TO) based on phase interpolation has been studied. It first employs injection-locked digitally-controlled ring oscillator (ILDRO) to obtain low phase noise high frequency fixed reference with multi-phase output. ΔΣ modulator (ΔΣM) is then applied to achieve phase interpolation for frequency tuning. This method enables the creation of low phase noise tunable high frequency reference that can be applied to a normal integer-N PLL. Implemented in UMC CMOS 65nm technology, the TO achieves frequency resolution of 0.2 kHz and phase noise lower than -120dBc/Hz@100kHz, while occupying an area of only 0.257mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"124 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86577935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A full-duplex wireless integrated transceiver for implant-to-air data communications 一种全双工无线集成收发器，用于植入式对空数据通信
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338430
S. Mirbozorgi, H. Bahrami, M. Sawan, L. Rusch, B. Gosselin
{"title":"A full-duplex wireless integrated transceiver for implant-to-air data communications","authors":"S. Mirbozorgi, H. Bahrami, M. Sawan, L. Rusch, B. Gosselin","doi":"10.1109/CICC.2015.7338430","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338430","url":null,"abstract":"This paper presents a novel fully integrated full-duplex data transceiver to support bidirectional high-data rate neural interfaces (electrical stimulation and neural recording). The transmitter (TX) and the receiver (RX) are designed to share a single implantable antenna. The TX generates IR-UWB based on edge combining, and the RX uses a novel ISM-2.4-GHz narrow-band OOK receiver. Separation between the TX and RX path is implemented by: 1) properly shaping the transmitted pulse, so its spectrum falls between 3.1 and 7 GHz UWB subband, and 2) carefully filtering the spectrum of the received waveform directly in the receiver low-noise amplifier (LNA), to avoid using a circulator or a diplexer (found in most full duplex systems). The receiver is designed to support downlink telemetry of neural stimulation applications with a data rate as high as 100 Mbps within a power budget of 5 mW. The transmitter is designed to support uplink back telemetry of neural recording applications with a data rate of up to 500 Mbps for power consumption of 5.4 mW and 10.8 mW for OOK and BPSK modulations, respectively (10.8 pJ/b). Measurement results obtained with biological tissues confirm full functionality of the fabricated full duplex transceiver. The total size of the chip is 0.8 mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"9 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84204788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing 一个功能齐全的90nm 8Mb STT MRAM演示器，具有修剪的参考细胞传感
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338359
J. DeBrosse, T. Maffitt, Yutaka Nakamura, G. Jan, P. Wang
{"title":"A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing","authors":"J. DeBrosse, T. Maffitt, Yutaka Nakamura, G. Jan, P. Wang","doi":"10.1109/CICC.2015.7338359","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338359","url":null,"abstract":"Spin Transfer Torque Magnetoresistive RAM (STT MRAM) has uniquely attractive write performance and endurance characteristics. Nonetheless, little STT MRAM circuit hardware data has been published [1-4]. This paper describes a fully-functional 90nm 8Mb STT MRAM, identifies and describes solutions to the primary circuit challenges, and includes considerable circuit hardware data.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"237 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80404637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A voltage doubling passive rectifier/regulator circuit for biomedical implants 一种用于生物医学植入物的倍压无源整流/稳压电路
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338428
Edward K. F. Lee
{"title":"A voltage doubling passive rectifier/regulator circuit for biomedical implants","authors":"Edward K. F. Lee","doi":"10.1109/CICC.2015.7338428","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338428","url":null,"abstract":"A circuit called prectulator is proposed in this paper. It utilizes the output transistor (M<sub>pr</sub>) of a linear regulator also as a passive rectifier for providing a regulated DC output from an AC input. The bulk voltage and the gate voltage (V<sub>g</sub>) of M<sub>pr</sub> are biased by an auxiliary rectifier and an error amplifier (A<sub>e</sub>), respectively. During startup and overload situations, overdriving M<sub>pr</sub> may occur and is prevented by limiting V<sub>g</sub> inside A<sub>e</sub>. Using this technique, a voltage doubling prectulator was implemented in a 0.18μm CMOS process. At 15MHz with a peak AC voltage of 3.6V, a power efficient of 87.7% and a voltage conversion ratio of 1.67 were achieved for a 6V output with a load power of 46.8mW.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"136 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85355190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Session 12 — Tutorial — beyond CMOS: Large area electronics-concepts and prospects 第12部分-教程-超越CMOS:大面积电子-概念和前景
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338469
R. Aitken, T. Iizuka
{"title":"Session 12 — Tutorial — beyond CMOS: Large area electronics-concepts and prospects","authors":"R. Aitken, T. Iizuka","doi":"10.1109/CICC.2015.7338469","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338469","url":null,"abstract":"Summary form only given. While the trend in CMOS semiconductor is to miniaturize the devices and circuits at affordable cost, the development of organic and thin film field-effect transistors is driven by their potential use in low-cost electronic circuits on large-area flexible substrates. Recent significant performance improvement in transistors for large-area electronics raises a lot of attractive applications such as new display, bio-array sensors, large-area flexible sensors, low-cost RFID tags, etc. This embedded tutorial discusses recent advances in the field of large area electronics including organic and thin film transistors in addition to CMOS.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"251 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73468112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells 一个16nm可配置的通栅位单元寄存器文件，用于量化pet与net通栅位单元的VMIN优势
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338444
Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, K. Bowman, David Hansquine
{"title":"A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells","authors":"Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, K. Bowman, David Hansquine","doi":"10.1109/CICC.2015.7338444","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338444","url":null,"abstract":"A 16nm configurable pass-gate bit-cell register file allows a direct comparison of NFET versus PFET pass-gate bit cells for early technology evaluation. The configurable pass gate enables either a transmission-gate (TG), an NFET pass gate, or a PFET pass gate. From silicon test-chip measurement, the register file with PFET pass-gate bit cells achieves a 33% minimum supply voltage (VMIN) reduction in a 16nm FinFET technology and a 40% VMIN reduction in an enhanced 16nm FinFET technology as compared to a register file with NFET pass-gate bit cells. Test-chip measurements highlight the superior benefits of the PFET drive current relative to the NFET drive current at low voltages. The VMIN improvement with a PFET pass-gate bit cell represents a paradigm-shift from traditional CMOS circuit-design practices.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"77 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89229228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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