A 51 pW reference-free capacitive-discharging oscillator architecture operating at 2.8 Hz

Abstract

This paper presents a gate-leakage-based Hz-range oscillator that achieves ultra-low-power frequency-stable operation in a small area via a capacitive-discharging architecture. By pre-charging two capacitors to VDD, and then allowing one to discharge through a temperature stable discharging path, an accurate clock period is generated independent of VDD and without a power-expensive reference. By exploiting the opposite temperature dependencies of different gate-leakage transistors, a stable oscillation frequency is achieved. Implemented in a 65 nm CMOS process, the proposed oscillator consumes 51 pW at 2.8 Hz. Across a temperature range of -40 °C to 60 °C, the oscillator deviates down to ±0.05% /°C, enabling an accurate, low-cost, low-power timing solution at Hz-range frequency.