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Dynamic waveform shaping for reconfigurable radiated periodic signal generation with picosecond time-widths 皮秒时间宽度可重构辐射周期信号生成的动态波形整形
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338411
Xue Wu, K. Sengupta
{"title":"Dynamic waveform shaping for reconfigurable radiated periodic signal generation with picosecond time-widths","authors":"Xue Wu, K. Sengupta","doi":"10.1109/CICC.2015.7338411","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338411","url":null,"abstract":"In this paper, a scalable architecture is presented which can generate and radiate reconfigurable periodic waveforms in free-space with picosecond time-widths. This is achieved by allowing radiated electromagnetic-fields of fundamental and multiple harmonic frequencies to combine in free-space with the right amplitudes and delays, and quasi-optically construct the time-domain waveform in the desired direction. In this paper, a 4-element array with integrated antennas is presented which is demonstrated to radiate pulse trains of 2.6 ps time-widths as well as pure tones and harmonic frequencies at 107.5 GHz (EIRP=4.5 dBm), 215 GHz (EIRP=5.0 dBm) and any combination of amplitudes and delays of these two harmonics to generate a set of reconfigurable waveforms in free space. No silicon lens or substrate thinning was employed. To the best of the authors' knowledge, this is the sharpest radiated pulses demonstrated in any IC technology. The chip is fabricated in 65nm LP CMOS process.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89987110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities 一种利用机器学习克服数据转换和模拟处理非理想性的癫痫检测IC
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338456
Jintao Zhang, Liechao Huang, Zhuo Wang, N. Verma
{"title":"A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities","authors":"Jintao Zhang, Liechao Huang, Zhuo Wang, N. Verma","doi":"10.1109/CICC.2015.7338456","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338456","url":null,"abstract":"This paper presents a seizure-detection system wherein the accuracy required of the analog frontend is substantially relaxed. Typically, readout of electroencephalogram (EEG) signals would dominate the energy of such a system, due to the precision (noise, linearity) requirements. The presented system performs data conversion and analog multiplication for EEG feature extraction via simple circuits to demonstrate that feature errors can be overcome by appropriate retraining of a classification model, using a machine-learning algorithm. This precludes the need to design a high-precision frontend. The prototype, in 32nm CMOS, results in features whose RMS error normalized to their ideal values is 1.16 (i.e. errors are larger than ideal values). An ideal implementation of the seizure detector exhibits sensitivity, latency, false alarms of 5/5, 2.0 sec., 8, respectively. The feature errors degrade this to 5/5, 3.6 sec., 443, causing high false alarms; but retraining of the classification model restores this to 5/5, 3.4 sec., 4.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"77 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78775132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technology 基于32nm SOI CMOS技术的0.6 v、30 ghz超谐波耦合六相压控振荡器
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338484
Dongseok Shin, S. Raman, Kwang-Jin Koh
{"title":"A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technology","authors":"Dongseok Shin, S. Raman, Kwang-Jin Koh","doi":"10.1109/CICC.2015.7338484","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338484","url":null,"abstract":"This paper presents a six-phase VCO using a superharmonic coupling technique. Three VCOs are coupled by an inductive network in their tail nodes to generate six-phase outputs. This network also serves as a tail noise filter in each VCO. Therefore, the proposed six-phase VCO can achieve better phase noise performance than typical multiphase topologies. The proposed VCO is implemented in 32nm SOI CMOS process with core area of 0.6×0.5mm2. The VCO can be tuned from 29.24 GHz to 31.56 GHz, a frequency tuning range of 7.6% at 0.6V supply. With each VCO consuming 1.52 mW DC power (4.56 mW total), the measured phase noise is -128 dBc/Hz at 10 MHz offset when VCO output frequency is 31.43 GHz, resulting in -191 dBc/Hz of FOM.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89142866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation 功率和面积效率高的10 × 10 Gb/s自引导收发器，采用40 nm CMOS，无参考和通道无关的操作
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338372
Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae
{"title":"A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation","authors":"Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae","doi":"10.1109/CICC.2015.7338372","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338372","url":null,"abstract":"A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for reference-less and lane-independent operation is presented. PI output clock signals that are phase locked to the input data are used for the voltage-controlled oscillator (VCO) frequency locking. The VCO clock signal is then redistributed to the PIs, which triggers bootstrapping between the VCO and PIs. Entire lanes operate independently as in VCO-based parallel reference-less designs, but without performance penalties and with power and area savings. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology, having receiver and transmitter figure-of-merits (mW/Gb/s) of 2.03 and 2.13, respectively.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"55 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74900606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sensors 用于近零功率传感器的14.4nW 122KHz双相电流模弛豫振荡器
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338396
Shanshan Dai, J. Rosenstein
{"title":"A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sensors","authors":"Shanshan Dai, J. Rosenstein","doi":"10.1109/CICC.2015.7338396","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338396","url":null,"abstract":"This paper presents a novel ultra-low-power dual-phase current-mode relaxation oscillator, which produces a 122 kHz digital clock and has total power consumption of 14.4 nW at 0.6 V. Its frequency dependence is 327 ppm/°C over a temperature range of -20° C to 100° C, and its supply voltage coefficient is ±3.0%/V from 0.6 V to 1.8 V. The proposed oscillator is fabricated in 0.18 μm CMOS technology and occupies 0.03 mm2. At room temperature it achieves a figure of merit of 120 pW/kHz, making it one of the most efficient relaxation oscillators reported to date.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75540501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Efficiency improvement techniques for RF power amplifiers in deep submicron CMOS 深亚微米CMOS射频功率放大器效率提升技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338449
A. Banerjee, R. Hezar, Lei Ding
{"title":"Efficiency improvement techniques for RF power amplifiers in deep submicron CMOS","authors":"A. Banerjee, R. Hezar, Lei Ding","doi":"10.1109/CICC.2015.7338449","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338449","url":null,"abstract":"Integration of RF power amplifier (PA) in CMOS technology can help to reduce total solution cost and achieve small form factor in modern communication systems. To improve overall efficiency of the power amplifier supporting modulated signals with very high peak-to-average power ratio (PAPR), new transmitter and PA architectures are being explored by researchers. This paper reviews some of our recent developments in CMOS based PA architectures including PWM based digital transmitter and outphasing power amplifier and presents a new multi-mode outphasing PA designed in 45 nm CMOS.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77836175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Holisitic device exploration for 7nm node 7nm节点整体器件探索
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338377
P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta, D. Mocuta, Z. Tokei, D. Verkest, A. Thean, A. Steegen
{"title":"Holisitic device exploration for 7nm node","authors":"P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta, D. Mocuta, Z. Tokei, D. Verkest, A. Thean, A. Steegen","doi":"10.1109/CICC.2015.7338377","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338377","url":null,"abstract":"In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78088386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Scaling analog circuits into deep nanoscale CMOS: Obstacles and ways to overcome them 将模拟电路扩展到深度纳米级CMOS:障碍和克服方法
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338394
P. Kinget
{"title":"Scaling analog circuits into deep nanoscale CMOS: Obstacles and ways to overcome them","authors":"P. Kinget","doi":"10.1109/CICC.2015.7338394","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338394","url":null,"abstract":"Analog circuits provide the critical interfaces between the digital world inside today's integrated circuits and the physical world. Semiconductor technology scaling driven by `Moore's Law' has resulted in a phenomenal scaling of the performance of digital processors and memory. Continuing design innovations have enabled the scaling of analog interfaces onto scaled CMOS technologies, even though device scaling is a mixed blessing for the analog designer. This paper reviews the scaling challenges for analog circuits ranging from fundamental to practical challenges. Design strategies are outlined that in principle can overcome the challenges and can help guide the search for new circuit paradigms. Several examples of innovative analog design paradigms are reviewed and the opportunities in highly scaled CMOS technologies are outlined.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"204 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80303271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Embedded cooling technologies for densely integrated electronic systems 用于密集集成电子系统的嵌入式冷却技术
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338365
Thomas E. Sarvey, Yang Zhang, Li Zheng, Paragkumar Thadesar, R. Gutala, Colman Cheung, Arifur Rahman, M. Bakir
{"title":"Embedded cooling technologies for densely integrated electronic systems","authors":"Thomas E. Sarvey, Yang Zhang, Li Zheng, Paragkumar Thadesar, R. Gutala, Colman Cheung, Arifur Rahman, M. Bakir","doi":"10.1109/CICC.2015.7338365","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338365","url":null,"abstract":"In modern integrated systems, interconnect and thermal management technologies have become two major limitations to system performance. In this paper, a number of technologies are presented to address these challenges. First, low-loss polymer-embedded vias are demonstrated in thick wafers compatible with microfluidics. Next, fluidic I/Os for delivery of fluid to microfluidic heat sinks are demonstrated in assembled 2.5D and 3D stacks. Then thermal coupling between dice in 2.5D and 3D systems is explored. Lastly, the utility of microfluidic cooling is demonstrated through an FPGA, built in a 28nm process, with a monolithically integrated microfluidic heat sink.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87033103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 4.6mW, 22dBm IIP3 all MOSCAP based 34–314MHz tunable continuous time filter in 65nm 一个4.6mW, 22dBm IIP3全MOSCAP基于34-314MHz可调谐连续时间滤波器，65nm
2015 IEEE Custom Integrated Circuits Conference (CICC) Pub Date : 2015-11-30 DOI: 10.1109/CICC.2015.7338402
Rakesh Kumar Palani, R. Harjani
{"title":"A 4.6mW, 22dBm IIP3 all MOSCAP based 34–314MHz tunable continuous time filter in 65nm","authors":"Rakesh Kumar Palani, R. Harjani","doi":"10.1109/CICC.2015.7338402","DOIUrl":"https://doi.org/10.1109/CICC.2015.7338402","url":null,"abstract":"A inverter based filter design is proposed that uses only MOSCAPs as filter capacitors. Further in the design the load capacitance compensates the negative feedback network allowing the majority of current to flow into the load. This results in an increase in the overall power efficiency. As a proof of concept, a 3rd order inverter based 34-314 MHz tunable continuous time channel select filter for software-defined radios is fabricated in TSMCs 65nm technology. By using the high density tunable MOSCAPs at a low swing node, the filter achieves an OIP3 of +25.24 dBm while drawing 4.2mA from a 1.1V supply and occupies an area of 0.007mm2. The measured intermodulation distortion varies by 5dB across a 120° variation in temperature and 6.5dB across a 200mV variation in power supply. Further, the filter presents a high impedance node at the input and a low impedance node at the output easing system integration.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87345432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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