P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta, D. Mocuta, Z. Tokei, D. Verkest, A. Thean, A. Steegen
{"title":"7nm节点整体器件探索","authors":"P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta, D. Mocuta, Z. Tokei, D. Verkest, A. Thean, A. Steegen","doi":"10.1109/CICC.2015.7338377","DOIUrl":null,"url":null,"abstract":"In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"12 1","pages":"1-5"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":"{\"title\":\"Holisitic device exploration for 7nm node\",\"authors\":\"P. Raghavan, M. Bardon, D. Jang, P. Schuddinck, D. Yakimets, J. Ryckaert, A. Mercha, N. Horiguchi, N. Collaert, A. Mocuta, D. Mocuta, Z. Tokei, D. Verkest, A. Thean, A. Steegen\",\"doi\":\"10.1109/CICC.2015.7338377\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.\",\"PeriodicalId\":6665,\"journal\":{\"name\":\"2015 IEEE Custom Integrated Circuits Conference (CICC)\",\"volume\":\"12 1\",\"pages\":\"1-5\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"30\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE Custom Integrated Circuits Conference (CICC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2015.7338377\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2015.7338377","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.
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