{"title":"390–640MHz tunable oscillator based on phase interpolation with −120dBc/Hz in-band noise","authors":"Xu Meng, Lianhong Zhou, Fujian Lin, C. Heng","doi":"10.1109/CICC.2015.7338451","DOIUrl":null,"url":null,"abstract":"A high frequency tunable oscillator (TO) based on phase interpolation has been studied. It first employs injection-locked digitally-controlled ring oscillator (ILDRO) to obtain low phase noise high frequency fixed reference with multi-phase output. ΔΣ modulator (ΔΣM) is then applied to achieve phase interpolation for frequency tuning. This method enables the creation of low phase noise tunable high frequency reference that can be applied to a normal integer-N PLL. Implemented in UMC CMOS 65nm technology, the TO achieves frequency resolution of 0.2 kHz and phase noise lower than -120dBc/Hz@100kHz, while occupying an area of only 0.257mm2.","PeriodicalId":6665,"journal":{"name":"2015 IEEE Custom Integrated Circuits Conference (CICC)","volume":"124 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE Custom Integrated Circuits Conference (CICC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2015.7338451","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A high frequency tunable oscillator (TO) based on phase interpolation has been studied. It first employs injection-locked digitally-controlled ring oscillator (ILDRO) to obtain low phase noise high frequency fixed reference with multi-phase output. ΔΣ modulator (ΔΣM) is then applied to achieve phase interpolation for frequency tuning. This method enables the creation of low phase noise tunable high frequency reference that can be applied to a normal integer-N PLL. Implemented in UMC CMOS 65nm technology, the TO achieves frequency resolution of 0.2 kHz and phase noise lower than -120dBc/Hz@100kHz, while occupying an area of only 0.257mm2.