一个16nm可配置的通栅位单元寄存器文件,用于量化pet与net通栅位单元的VMIN优势

Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, K. Bowman, David Hansquine
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引用次数: 1

摘要

16nm可配置通栅极位单元寄存器文件允许直接比较NFET和pet通栅极位单元,用于早期技术评估。可配置的通闸可以启用传输门(TG)、fet通闸或fet通闸。从硅测试芯片的测量结果来看,与具有fet通栅极位单元的寄存器文件相比,具有fet通栅极位单元的寄存器文件在16nm FinFET技术中实现了33%的最小电源电压(VMIN)降低,在增强型16nm FinFET技术中实现了40%的VMIN降低。测试芯片的测量结果显示,相对于低电压下的fet驱动电流,fet驱动电流具有更优越的优势。采用pet通栅位单元的VMIN改进代表了传统CMOS电路设计实践的范式转变。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells
A 16nm configurable pass-gate bit-cell register file allows a direct comparison of NFET versus PFET pass-gate bit cells for early technology evaluation. The configurable pass gate enables either a transmission-gate (TG), an NFET pass gate, or a PFET pass gate. From silicon test-chip measurement, the register file with PFET pass-gate bit cells achieves a 33% minimum supply voltage (VMIN) reduction in a 16nm FinFET technology and a 40% VMIN reduction in an enhanced 16nm FinFET technology as compared to a register file with NFET pass-gate bit cells. Test-chip measurements highlight the superior benefits of the PFET drive current relative to the NFET drive current at low voltages. The VMIN improvement with a PFET pass-gate bit cell represents a paradigm-shift from traditional CMOS circuit-design practices.
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