2012 International Electron Devices Meeting最新文献_第5页

Monolithic integration of GaN-based micromechanical resonators and HEMTs for timing applications 基于氮化镓的微机械谐振器和用于定时应用的hemt的单片集成

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479049

A. Ansari, V. Gokhale, J. Roberts, M. Rais-Zadeh

引用次数: 26

Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device 利用双栅薄膜晶体管(TFT)器件对窄间距垂直栅极3D NAND闪存的随机晶界和陷阱位置诱导的不对称读取行为进行了建模

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479111

Y. Hsiao, H. Lue, Wei-Chen Chen, Chih-Ping Chen, Kuo-Ping Chang, Y. Shih, B. Tsui, Chih-Yuan Lu

{"title":"Modeling the variability caused by random grain boundary and trap-location induced asymmetrical read behavior for a tight-pitch vertical gate 3D NAND Flash memory using double-gate thin-film transistor (TFT) device","authors":"Y. Hsiao, H. Lue, Wei-Chen Chen, Chih-Ping Chen, Kuo-Ping Chang, Y. Shih, B. Tsui, Chih-Yuan Lu","doi":"10.1109/IEDM.2012.6479111","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479111","url":null,"abstract":"The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"26.7.1-26.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90661399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

Engineering grains of Ge2Sb2Te5 for realizing fast-speed, low-power, and low-drift phase-change memories with further multilevel capabilities Ge2Sb2Te5的工程颗粒，用于实现具有进一步多电平功能的快速，低功耗和低漂移相变存储器

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479143

W. J. Wang, D. Loke, L. Law, L. P. Shi, R. Zhao, M. Li, L. L. Chen, H. Yang, Y. Yeo, A. Adeyeye, T. Chong, A. Lacaita

引用次数: 14

A highly integrated 65-nm SoC process with enhanced power/performance of digital and analog circuits 高度集成的65纳米SoC工艺，增强了数字和模拟电路的功率/性能

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479042

L. Clark, D. Zhao, T. Bakhishev, H. Ahn, E. Boling, M. Duane, K. Fujita, P. Gregory, T. Hoffmann, M. Hori, D. Kanai, D. Kidd, S. Lee, Y. Liu, J. Mitani, J. Nagayama, S. Pradhan, P. Ranade, R. Rogenmoser, L. Scudder, L. Shifren, Y. Torii, M. Wojko, Y. Asada, T. Ema, S. Thompson

引用次数: 21

A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications 采用3-D三栅极和高k/金属栅极的22nm SoC平台技术，针对超低功耗、高性能和高密度SoC应用进行了优化

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478969

Chia-Hong Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, Walid M. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, Park Joodong, K. Phoa, Arifur Rahman, C. Staus, H. Tashiro, Tsai Curtis, P. Vandervoorn, Laurence T. Yang, J. Yeh, P. Bai

{"title":"A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications","authors":"Chia-Hong Jan, U. Bhattacharya, R. Brain, S. Choi, G. Curello, G. Gupta, Walid M. Hafez, M. Jang, M. Kang, K. Komeyli, T. Leo, N. Nidhi, L. Pan, Park Joodong, K. Phoa, Arifur Rahman, C. Staus, H. Tashiro, Tsai Curtis, P. Vandervoorn, Laurence T. Yang, J. Yeh, P. Bai","doi":"10.1109/IEDM.2012.6478969","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478969","url":null,"abstract":"A leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time. Low standby power and high voltage transistors exploiting the superior short channel control, <; 65mV/dec subthreshold slope and <;40mV DIBL, of the Tri-Gate architecture have been fabricated concurrently with high speed logic transistors in a single SoC chip to achieve industry leading drive currents at record low leakage levels. NMOS/PMOS Idsat=0.41/0.37mA/um at 30pA/um Ioff, 0.75V, were used to build a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages. This technology offers mix-and-match flexibility of transistor types, high-density interconnect stacks, and RF/mixed-signal features for leadership in mobile, handheld, wireless and embedded SoC products.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"32 1","pages":"3.1.1-3.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74409795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 278

Towards atomistic simulations of the electro-thermal properties of nanowire transistors 纳米线晶体管电热特性的原子模拟

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479057

M. Luisier

引用次数: 1

Triangular-channel Ge NFETs on Si with (111) sidewall-enhanced Ion and nearly defect-free channels 具有(111)侧壁增强离子和几乎无缺陷通道的硅基三角形沟道Ge非场效应管

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479090

Shu‐Han Hsu, Hung-Chih Chang, C. Chu, Yen‐Ting Chen, W. Tu, F. Hou, Chih-hung Lo, P. Sung, Bo-Yuan Chen, G. Huang, G. Luo, Cheewee Liu, C. Hu, Fu-Liang Yang

引用次数: 17

Highly endurable floating body cell memory: Vertical biristor 高度耐用的浮动体细胞记忆:垂直历史

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479147

Dong-il Moon, Sung-Jin Choi, Jee-Yeon Kim, Seungwon Ko, Moon-Seok Kim, J. Oh, G. Lee, Min-Ho Kang, Young-Su Kim, J. Kim, Yang‐Kyu Choi

引用次数: 16

Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics 采用AlON高k栅极电介质提高SiC功率mosfet的性能和可靠性

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478998

T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe

引用次数: 25

GaN Gate Injection Transistor with integrated Si Schottky barrier diode for highly efficient DC-DC converters 集成硅肖特基势垒二极管的GaN栅注入晶体管，用于高效DC-DC变换器

2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478996

T. Morita, S. Ujita, H. Umeda, Y. Kinoshita, S. Tamura, Y. Anda, T. Ueda, T. Tanaka

引用次数: 31