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Microscopic understanding and modeling of HfO2 RRAM device physics HfO2 RRAM器件物理的微观理解和建模
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479077
L. Larcher, A. Padovani, O. Pirrotta, L. Vandelli, G. Bersuker
{"title":"Microscopic understanding and modeling of HfO2 RRAM device physics","authors":"L. Larcher, A. Padovani, O. Pirrotta, L. Vandelli, G. Bersuker","doi":"10.1109/IEDM.2012.6479077","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479077","url":null,"abstract":"In this paper we investigate the physical mechanisms governing operations in HfOx RRAM devices. Forming set and reset processes are studied using a model including power dissipation associated with the charge transport, and the corresponding temperature increase, which assists ion diffusion.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"441 1","pages":"20.1.1-20.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79638338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Characterization of traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT 嵌入式栅极常关AlGaN/ gan基MOSHEMT中陷阱及其相关效应的表征
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479034
J. Bae, I. Hwang, Jongmin Shin, H. Kwon, C. Park, J. Ha, Jaewon Lee, Hyoji Choi, Jongseob Kim, Jong-bong Park, Jae-joon Oh, Jaikwang Shin, U. Chung, Jong-Ho Lee
{"title":"Characterization of traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT","authors":"J. Bae, I. Hwang, Jongmin Shin, H. Kwon, C. Park, J. Ha, Jaewon Lee, Hyoji Choi, Jongseob Kim, Jong-bong Park, Jae-joon Oh, Jaikwang Shin, U. Chung, Jong-Ho Lee","doi":"10.1109/IEDM.2012.6479034","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479034","url":null,"abstract":"Traps and trap-related effects in recessed-gate normally-off AlGaN/GaN-based MOSHEMT with SiO2 gate dielectric were characterized. Hysteresis in ID-VG was observed at elevated temperature (~120°C) due to the traps. To understand the traps, current transient in drain was investigated at given gate and drain pulses with different temperatures. Two groups of time constants were extracted: one is nearly constant and the other is decreased with temperature. Extracted activation energies from the drain current transients with temperature are 0.66 eV and 0.73 eV, respectively, for given gate and drain pulses. Using extracted exponential trap density profile from frequency dependent conductance method [4], we could understand C-V behavior with frequency. It was shown that traps inside AlGaN layer are a main cause for the decrease of capacitance at high frequency in inversion region. The pulsed I-V characteristics also show frequency dependence.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"24 1","pages":"13.2.1-13.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89330618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
The role of silicon, silicon carbide and gallium nitride in power electronics 硅、碳化硅和氮化镓在电力电子中的作用
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478995
M. Treu, E. Vecino, M. Pippan, O. Haberlen, G. Curatola, G. Deboy, M. Kutschak, U. Kirchner
{"title":"The role of silicon, silicon carbide and gallium nitride in power electronics","authors":"M. Treu, E. Vecino, M. Pippan, O. Haberlen, G. Curatola, G. Deboy, M. Kutschak, U. Kirchner","doi":"10.1109/IEDM.2012.6478995","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478995","url":null,"abstract":"Silicon carbide (SiC) and latest gallium nitride (GaN) are two semiconductor materials which entered the power device arena which has been set up and still is being dominated by silicon based devices. The following paper will make a basic comparison of power devices out of these three base materials valid for medium voltage classes of some hundred to above 1000V. This paper will start with comparisons of common electrical figures of merit (FOM) and will focus less on the exact values but on the possible trends and current limits concerning the different materials. These findings will be brought in relation to application requirements.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"71 1","pages":"7.1.1-7.1.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85134061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Improving analog/RF performance of multi-gate devices through multi-dimensional design optimization with awareness of variations and parasitics 通过多维度设计优化，提高多栅极器件的模拟/射频性能
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479043
Yuchao Liu, Ru Huang, Runsheng Wang, Jiaojiao Ou, Yangyuan Wang
{"title":"Improving analog/RF performance of multi-gate devices through multi-dimensional design optimization with awareness of variations and parasitics","authors":"Yuchao Liu, Ru Huang, Runsheng Wang, Jiaojiao Ou, Yangyuan Wang","doi":"10.1109/IEDM.2012.6479043","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479043","url":null,"abstract":"In this paper, a new design optimization method is put forward, which can significantly improve the analog/RF performance of MG devices with impacts of parasitics and process variations considered. The gate-all-around silicon nanowire transistors (SNWTs) are taken as example, the analog/RF performance, such as cutoff frequency (fT), transconductance efficiency (gm/Id), intrinsic gain (gm/gds) and comprehensive figure of merit (FOM) are optimized by utilizing the proposed method. Through design optimization, higher fT of SNWTs can be obtained compared with planar FETs, which can approach the ITRS projection, manifesting the promising potential of SNWTs for high frequency circuit applications. The optimal regions of independent variable vector (X) of SNWTs are given, which can provide useful guidelines for MG device-based circuit design.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"21 1","pages":"14.5.1-14.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90157161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Spin transport in metal and oxide devices at the nanoscale 纳米级金属和氧化物器件中的自旋输运
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479024
S. Parui, K. Rana, T. Banerjee
{"title":"Spin transport in metal and oxide devices at the nanoscale","authors":"S. Parui, K. Rana, T. Banerjee","doi":"10.1109/IEDM.2012.6479024","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479024","url":null,"abstract":"Here we discuss a non-destructive technique that characterizes spin and charge transport at the nanometer scale, across buried layers and interfaces, in magnetic memory elements as used in spin transfer torque based Magnetic Random Access Memory (STT-MRAM). While probing in the current-perpendicular-to-plane direction, this method enables quantification of essential spin transport parameters as length and time scale, spin polarization in buried layers and interfaces, visualization of domain wall evolution across buried interfaces, besides investigating the homogeneity of transport, at the nanoscale, in spintronics devices.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"135 1","pages":"11.4.1-11.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79543218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration 三维类铁电NVM/CMOS混合芯片，采用低于400°C的顺序分层集成
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479160
Yu-Chung Lien, J. Shieh, Wen-Hsien Huang, Wei-Shang Hsieh, Cheng-Hui Tu, Chieh-An Wang, C. Shen, T. Chou, Min-Cheng Chen, J. Y. Huang, C. Pan, Y. Lai, C. Hu, Fu-Liang Yang
{"title":"3D Ferroelectric-like NVM/CMOS hybrid chip by sub-400 °C sequential layered integration","authors":"Yu-Chung Lien, J. Shieh, Wen-Hsien Huang, Wei-Shang Hsieh, Cheng-Hui Tu, Chieh-An Wang, C. Shen, T. Chou, Min-Cheng Chen, J. Y. Huang, C. Pan, Y. Lai, C. Hu, Fu-Liang Yang","doi":"10.1109/IEDM.2012.6479160","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479160","url":null,"abstract":"For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm2/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400°C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed data-storage application era.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"18 1","pages":"33.6.1-33.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77977677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Improved thermal conductivity by vertical graphene contact formation for thermal TSV 通过垂直石墨烯接触形成热TSV提高热导率
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479159
M. Nihei, A. Kawabata, T. Murakami, M. Sato, N. Yokoyama
{"title":"Improved thermal conductivity by vertical graphene contact formation for thermal TSV","authors":"M. Nihei, A. Kawabata, T. Murakami, M. Sato, N. Yokoyama","doi":"10.1109/IEDM.2012.6479159","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479159","url":null,"abstract":"This paper reports the tailoring thermal conductivity of novel dense vertical and horizontal graphene (DVHG) structures, which we previously discovered. By removing horizontal graphene layers, resulting in forming vertical graphene contacts to the electrode, we not only improved the thermal conductivity by a factor of 10 but also improved the electrical conductivity by a factor of 100. The pyrolytic graphite, grown at a higher temperature than the DVHG, showed a high thermal conductivity of 1426 W/mK by forming vertical graphene contacts. Although the DVHG showed poor thermal properties at this point, we found that the vertical graphene contact formation can be an important technology to realize high thermal conductivity for carbon-based thermal through-silicon-vias (TSV).","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"42 1","pages":"33.5.1-33.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85085675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A physical based analytic model of RRAM operation for circuit simulation 用于电路仿真的基于物理的RRAM运行分析模型
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479110
P. Huang, X. Liu, W. H. Li, Y. X. Deng, B. Chen, Y. Lu, B. Gao, L. Zeng, K. Wei, G. Du, X. Zhang, J. Kang
{"title":"A physical based analytic model of RRAM operation for circuit simulation","authors":"P. Huang, X. Liu, W. H. Li, Y. X. Deng, B. Chen, Y. Lu, B. Gao, L. Zeng, K. Wei, G. Du, X. Zhang, J. Kang","doi":"10.1109/IEDM.2012.6479110","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479110","url":null,"abstract":"A physical based analytic model of metal oxide based RRAM cell under DC and pulse operation modes is presented. In this model, the transport behaviors of oxygen vacancies and oxygen ions, metal conductivity, electron hopping and heat conduction and the parasitic capacitance and resistance effects are covered. The developed analytic model is verified and calibrated by measured data. Furthermore, we implement the analytic model in a 2×2 RRAM array simulation and investigate the reliability of RRAM array for the first time.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"78 1","pages":"26.6.1-26.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85575245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Device considerations for high density and highly reliable 3D NAND flash cell in near future 在不久的将来，高密度和高可靠的3D NAND闪存单元的器件考虑
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479011
Eun-seok Choi, Sung-Kye Park
{"title":"Device considerations for high density and highly reliable 3D NAND flash cell in near future","authors":"Eun-seok Choi, Sung-Kye Park","doi":"10.1109/IEDM.2012.6479011","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479011","url":null,"abstract":"Recently, we have suggested highly manufacturable and reliable 3D NAND flash cell called “SMArT”[1], which is intended to minimize both stack height and word line resistance. Because the storage node of this cell is charge trap nitride, its device characteristics were far different from conventional floating gate. In this paper, the key cell characteristics such as cell Vth distribution, disturbance, and reliability are compared with our FG cell of 2y node in chip level, and several future challenges for 3D era will be addressed.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"9.4.1-9.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88565439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
RRAM SET speed-disturb dilemma and rapid statistical prediction methodology RRAM SET速度干扰困境与快速统计预测方法
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479012
Wun-Cheng Luo, Jen-Chieh Liu, Hsien-Tsung Feng, Yen-Chuan Lin, Jiun-Jia Huang, Kuan-Liang Lin, T. Hou
{"title":"RRAM SET speed-disturb dilemma and rapid statistical prediction methodology","authors":"Wun-Cheng Luo, Jen-Chieh Liu, Hsien-Tsung Feng, Yen-Chuan Lin, Jiun-Jia Huang, Kuan-Liang Lin, T. Hou","doi":"10.1109/IEDM.2012.6479012","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479012","url":null,"abstract":"This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"25 1","pages":"9.5.1-9.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89084641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
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