Improving analog/RF performance of multi-gate devices through multi-dimensional design optimization with awareness of variations and parasitics

Abstract

In this paper, a new design optimization method is put forward, which can significantly improve the analog/RF performance of MG devices with impacts of parasitics and process variations considered. The gate-all-around silicon nanowire transistors (SNWTs) are taken as example, the analog/RF performance, such as cutoff frequency (fT), transconductance efficiency (gm/Id), intrinsic gain (gm/gds) and comprehensive figure of merit (FOM) are optimized by utilizing the proposed method. Through design optimization, higher fT of SNWTs can be obtained compared with planar FETs, which can approach the ITRS projection, manifesting the promising potential of SNWTs for high frequency circuit applications. The optimal regions of independent variable vector (X) of SNWTs are given, which can provide useful guidelines for MG device-based circuit design.