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Highly-scalable threshold switching select device based on chaclogenide glasses for 3D nanoscaled memory arrays 基于chlogenide玻璃的高可扩展阈值开关选择器件，用于3D纳米级存储阵列
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478966
Myoung-Jae Lee, Dongsoo Lee, Hojung Kim, Hyun-Sik Choi, Jong-bong Park, Hee-Goo Kim, Y. Cha, U. Chung, I. Yoo, Kinam Kim
{"title":"Highly-scalable threshold switching select device based on chaclogenide glasses for 3D nanoscaled memory arrays","authors":"Myoung-Jae Lee, Dongsoo Lee, Hojung Kim, Hyun-Sik Choi, Jong-bong Park, Hee-Goo Kim, Y. Cha, U. Chung, I. Yoo, Kinam Kim","doi":"10.1109/IEDM.2012.6478966","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478966","url":null,"abstract":"We present here on a switch device made of a nitridized-chalcogenide glass for application in nanoscale array circuits. Previously, AsTeGeSi-based switches have had key issues with performance degradation over time. This is usually due to changes in the Te concentration in the device active region [1-3]. However, our AsTeGeSiN switches were able to overcome this limitation as well as scale down to 30 nm with an on current of 100 μA (J > 1.1×107A/cm2). Their cycling performance was shown to be greater than 108. Also, we demonstrate a memory cell using a TaOx resistance memory with the AsTeGeSiN select device.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"53 1","pages":"2.6.1-2.6.3"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83827805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Ultra low power design and future device interactions 超低功耗设计和未来设备交互
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478972
A. Amerasekera, C. Bittlestone
{"title":"Ultra low power design and future device interactions","authors":"A. Amerasekera, C. Bittlestone","doi":"10.1109/IEDM.2012.6478972","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478972","url":null,"abstract":"We present the interactions between the process technology and the design that set the requirements for ultra low power and mixed signal circuits and chips that form the basis of the next generations of semiconductor applications.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"4 1","pages":"3.4.1-3.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80818724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts 一种高度可扩展的8层垂直栅极3D NAND，具有分页位线布局和高效的二进制和MiLC(最小增量层成本)阶梯触点
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6478963
Shih-Hung Chen, H. Lue, Y. Shih, Chieh-Fang Chen, T. Hsu, Yan-Ru Chen, Y. Hsiao, Shih-Cheng Huang, Kuo-Pin Chang, C. Hsieh, Guan-Ru Lee, A. Chuang, Chih-Wei Hu, C. Chiu, Lo-Yueh Lin, Hong-Ji Lee, F. Tsai, Chin-Cheng Yang, Tahone Yang, Chih-Yuan Lu
{"title":"A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts","authors":"Shih-Hung Chen, H. Lue, Y. Shih, Chieh-Fang Chen, T. Hsu, Yan-Ru Chen, Y. Hsiao, Shih-Cheng Huang, Kuo-Pin Chang, C. Hsieh, Guan-Ru Lee, A. Chuang, Chih-Wei Hu, C. Chiu, Lo-Yueh Lin, Hong-Ji Lee, F. Tsai, Chin-Cheng Yang, Tahone Yang, Chih-Yuan Lu","doi":"10.1109/IEDM.2012.6478963","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6478963","url":null,"abstract":"We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BL's (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"145 1","pages":"2.3.1-2.3.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80480625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Exceeding Nernst limit (59mV/pH): CMOS-based pH sensor for autonomous applications 超过能量限制(59mV/pH):基于cmos的pH传感器，用于自主应用
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479098
K. B. Parizi, A. J. Yeh, A. Poon, H. Wong
{"title":"Exceeding Nernst limit (59mV/pH): CMOS-based pH sensor for autonomous applications","authors":"K. B. Parizi, A. J. Yeh, A. Poon, H. Wong","doi":"10.1109/IEDM.2012.6479098","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479098","url":null,"abstract":"A highly sensitive field-effect sensor immune to environmental potential fluctuation is proposed. The sensor circuit consists of two sensors each with a charge sensing field effect transistor (FET) and an extended sensing gate (SG). By enlarging the sensing gate of an extended gate ISFET, a remarkable sensitivity of 130mV/pH is achieved, exceeding the conventional Nernst limit of 59mV/pH. The proposed differential sensing circuit consists of a pair of matching n-channel and p-channel ion sensitive sensors connected in parallel and biased at a matched transconductance bias point. Potential fluctuations in the electrolyte appear as common mode signal to the differential pair and are cancelled by the matched transistors. This novel differential measurement technique eliminates the need for a true reference electrode such as the bulky Ag/AgCl reference electrode and enables the use of the sensor for autonomous and implantable applications.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"36 1","pages":"24.7.1-24.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83208056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch 利用互补原子开关在非易失性可编程单元上的逻辑映射首次演示
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479020
M. Miyamura, M. Tada, T. Sakamoto, N. Banno, K. Okamoto, N. Iguchi, H. Hada
{"title":"First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch","authors":"M. Miyamura, M. Tada, T. Sakamoto, N. Banno, K. Okamoto, N. Iguchi, H. Hada","doi":"10.1109/IEDM.2012.6479020","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479020","url":null,"abstract":"Reconfigurable nonvolatile programmable logic using complementary atom switch (CAS) is successfully demonstrated on a 65-nm-node test chip. Various logics are realized by synthesizing RTL codes and mapping the configurations into CAS-based programmable cell array. Each cell includes the two 4-input LUTs, 19×16 crossbar switch, and 368-b CAS. The CAS integrated over CMOS reduces the cell area by 78% compared to a conventional SRAM-based design.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"107 1","pages":"10.6.1-10.6.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77815429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 35
E-mode planar Lg = 35 nm In0.7Ga0.3As MOSFETs with InP/Al2O3/HfO2 (EOT = 0.8 nm) composite insulator 采用InP/Al2O3/HfO2 (EOT = 0.8 nm)复合绝缘体的平面Lg = 35 nm In0.7Ga0.3As mosfet
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479150
D. Kim, P. Hundal, A. Papavasiliou, P. Chen, C. King, J. Paniagua, M. Urteaga, B. Brar, Y. G. Kim, J. Kuo, J. Li, P. Pinsukanjana, Y. Kao
{"title":"E-mode planar Lg = 35 nm In0.7Ga0.3As MOSFETs with InP/Al2O3/HfO2 (EOT = 0.8 nm) composite insulator","authors":"D. Kim, P. Hundal, A. Papavasiliou, P. Chen, C. King, J. Paniagua, M. Urteaga, B. Brar, Y. G. Kim, J. Kuo, J. Li, P. Pinsukanjana, Y. Kao","doi":"10.1109/IEDM.2012.6479150","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479150","url":null,"abstract":"We have successfully demonstrated a three-step recess process to fabricate high performance E-mode planar InGaAs MOSFETs. Our devices feature a composite gate insulator with InP/Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>. An L<sub>g</sub>=35 nm InGaAs MOSFET with EOT = ~ 0.8 nm exhibits V<sub>T</sub> = 0.17 V, R<sub>ON</sub> = 285 Ohm-μm, DIBL = 135 mV/V and S = 115 mV/dec, as well as a negligible dispersion and hysteresis behavior. Most importantly, our device displays the highest value of g<sub>m_max</sub> > 2 mS/μm at V<sub>DS</sub> = 0.5 V in any III-V MOSFETs.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"18 1","pages":"32.2.1-32.2.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90067357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
High photocurrent and quantum efficiency of graphene photodetector using layer-by-layer stack structure and trap assistance 利用层层堆叠结构和陷阱辅助的高光电流和量子效率的石墨烯光电探测器
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479096
Hua-Min Li, Tian-zi Shen, Daeyeong Lee, W. Yoo
{"title":"High photocurrent and quantum efficiency of graphene photodetector using layer-by-layer stack structure and trap assistance","authors":"Hua-Min Li, Tian-zi Shen, Daeyeong Lee, W. Yoo","doi":"10.1109/IEDM.2012.6479096","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479096","url":null,"abstract":"Two approaches, graphene stack (GS) structure assembled by layer-by-layer (LBL) transfer and trap assistant technique for single-layer graphene (SLG), are applied to field-effect transistors (FETs) for photodetection. In LBL-GS-FET, about 3.6 times increased photocurrent (PC) together with increased internal/external quantum efficiency (IQE/EQE) is obtained compared to the conventional SLG-FET, owing to an improvement of both electrical transport and optical absorption. In trap-assisted SLG-FET, the PC over 12% compared to the dark current with the superior photo-responsivity (S) of 2.8 mA/W and the IQE/EQE of 23.0%/ 0.5% is obtained, due to the different response of trapping effect in dark and illumination environments.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"87 1","pages":"24.5.1-24.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86691038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI 用于NBTI和PBTI无恢复评估的32nm SRAM可靠性宏
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479014
P. Jain, A. Paul, Xiaofei Wang, C. Kim
{"title":"A 32nm SRAM reliability macro for recovery free evaluation of NBTI and PBTI","authors":"P. Jain, A. Paul, Xiaofei Wang, C. Kim","doi":"10.1109/IEDM.2012.6479014","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479014","url":null,"abstract":"A scalable test structure for recovery free evaluation of the impact of NBTI and PBTI on read/write operation in a SRAM macro has been developed. A novel non-invasive methodology keeps the stress interrupts for measurements within a few microseconds, preventing unwanted BTI recovery, while providing a parallel stress-measure capability on 32kb sub-arrays. Measurement results in a 32nm high-κ/metal-gate silicon-on-insulator process show that proposed schemes provides 35mV better accuracy in read VMIN and 10X accuracy in BFR.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"9.7.1-9.7.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87792505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration 基于条纹栅极结构的结耗尽调制，具有36mV/dec亚阈值斜率的新型硅隧道场效应管
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479005
Qianqian Huang, Ru Huang, Zhan Zhan, Y. Qiu, Wenzhe Jiang, Chunlei Wu, Yangyuan Wang
{"title":"A novel Si tunnel FET with 36mV/dec subthreshold slope based on junction depleted-modulation through striped gate configuration","authors":"Qianqian Huang, Ru Huang, Zhan Zhan, Y. Qiu, Wenzhe Jiang, Chunlei Wu, Yangyuan Wang","doi":"10.1109/IEDM.2012.6479005","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479005","url":null,"abstract":"In this paper, a novel junction depleted-modulation design to achieve equivalently abrupt tunnel junction of Si Tunnel FET (TFET) is proposed. By changing the gate layout configuration, the new Junction-modulated TFET can reliably and effectively achieve much steeper switching behavior and higher ON current without area penalty and special fabrication compared with traditional TFET. Further junction optimization by introducing the self-depleted doping pocket with much relaxed process requirements is also experimentally demonstrated based on the bulk Si substrate. With traditional Si CMOS-compatible process, the fabricated device shows a minimum substhreshold slope of 36mV/dec within one decade of drain current.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"1 1","pages":"8.5.1-8.5.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88507424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 112
Uniform methodology for benchmarking beyond-CMOS logic devices 超越cmos逻辑器件基准测试的统一方法
2012 International Electron Devices Meeting Pub Date : 2012-12-01 DOI: 10.1109/IEDM.2012.6479102
D. Nikonov, I. Young
{"title":"Uniform methodology for benchmarking beyond-CMOS logic devices","authors":"D. Nikonov, I. Young","doi":"10.1109/IEDM.2012.6479102","DOIUrl":"https://doi.org/10.1109/IEDM.2012.6479102","url":null,"abstract":"A consistent methodology for benchmarking beyond CMOS logic devices was developed to guide the research directions. The promising devices - tunneling FET and spin wave devices - perform > 10<sup>15</sup> Integer Ops/s/cm<sup>2</sup> with power <; 1W/cm<sup>2</sup>.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"38 8","pages":"25.4.1-25.4.4"},"PeriodicalIF":0.0,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91455549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 82
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