T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe
{"title":"采用AlON高k栅极电介质提高SiC功率mosfet的性能和可靠性","authors":"T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe","doi":"10.1109/IEDM.2012.6478998","DOIUrl":null,"url":null,"abstract":"We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"240 1","pages":"7.4.1-7.4.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":"{\"title\":\"Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics\",\"authors\":\"T. Hosoi, Shuji Azumo, Yusaku Kashiwagi, S. Hosaka, R. Nakamura, Shuhei Mitani, Y. Nakano, H. Asahara, Takashi Nakamura, Tsunenobu Kimoto, T. Shimura, Heiji Watanabe\",\"doi\":\"10.1109/IEDM.2012.6478998\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.\",\"PeriodicalId\":6376,\"journal\":{\"name\":\"2012 International Electron Devices Meeting\",\"volume\":\"240 1\",\"pages\":\"7.4.1-7.4.4\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"25\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2012.6478998\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6478998","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance and reliability improvement in SiC power MOSFETs by implementing AlON high-k gate dielectrics
We have developed AlON high-k gate dielectric technology that can be easily implemented into both planar and trench SiC-based MOSFETs. On the basis of electrical characterization and numerical simulation, the thickness ratio of the AlON layer to the SiO2 interlayer and nitrogen content in AlON film were carefully optimized to enhance device performance and reliability.