W. J. Wang, D. Loke, L. Law, L. P. Shi, R. Zhao, M. Li, L. L. Chen, H. Yang, Y. Yeo, A. Adeyeye, T. Chong, A. Lacaita
{"title":"Engineering grains of Ge2Sb2Te5 for realizing fast-speed, low-power, and low-drift phase-change memories with further multilevel capabilities","authors":"W. J. Wang, D. Loke, L. Law, L. P. Shi, R. Zhao, M. Li, L. L. Chen, H. Yang, Y. Yeo, A. Adeyeye, T. Chong, A. Lacaita","doi":"10.1109/IEDM.2012.6479143","DOIUrl":null,"url":null,"abstract":"Phase-change memory (PCM) represents one of the best candidates for a “universal memory”. However, its slow SET speed, high RESET power, and high resistance drift present key challenges towards this ambition. Here, grain-engineered Ge2Sb2Te5 is exploited to control the crystallization kinetics, and electrical properties of PCM. We report 120 % higher SET speeds with respect to conventional scaling. Good stability (140°C), 30 % RESET power reduction, and 2X lower resistance drift were also achieved. A 4-state/2-bit multilevel cell was further demonstrated. This provides a route to making high-density PCM devices.","PeriodicalId":6376,"journal":{"name":"2012 International Electron Devices Meeting","volume":"3 1","pages":"31.3.1-31.3.4"},"PeriodicalIF":0.0000,"publicationDate":"2012-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2012.6479143","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
Phase-change memory (PCM) represents one of the best candidates for a “universal memory”. However, its slow SET speed, high RESET power, and high resistance drift present key challenges towards this ambition. Here, grain-engineered Ge2Sb2Te5 is exploited to control the crystallization kinetics, and electrical properties of PCM. We report 120 % higher SET speeds with respect to conventional scaling. Good stability (140°C), 30 % RESET power reduction, and 2X lower resistance drift were also achieved. A 4-state/2-bit multilevel cell was further demonstrated. This provides a route to making high-density PCM devices.